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Download docs - Car wirings and schematics,automobile documentation, auto repair guides,car audio manuals, car stereo| File information: | | File name: | vss.rar
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| | Original Chassis: | | | Descr: | VSS
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| Information about the files in archive: | | Decompress result: | OK | | Extracted files: | 3 | | File name | | Text | | BD_V3_L3_C_A3_V1[1].2.pdf | | RX MID CHANNELS 850: CH190 -- 881,6 GSM: CH 62 -- 947,4 MHz EGSM: CH 37 -- 942,4Mhz DCS: CH 700 -- 1842,8MHz PCS: CH 661 -- 1960MHz
TRK_OSC_OUT ( 26MHz for Digital IF Filter syncronisation) 35 19 20 22 23 16 17 High Band 1800 MHz Low Band 850 MHz 13 14
NEPTUNE LTS
U800
Tracking Control
100kHz
U150
LNA
ALGAE
AGC RF Det.
L&H Band
B5 27 BB Out 28 26 29 BB Out 30 CM IN BB I BB IX (decoupling analog GND) BB Q BB QX RF REG 47 RX Loop Filter RX_CP RF_5V_REG SYNTH_FD_P SYNTH_FB_N TX_CP 44 TX Loop Filter TX_MOD 26 MHz 3 A8 B8
Tracking Osc.
N
DSP Peripherals accelerator, encryption Timer, Interupts DMA Direct Memory Access Controller
POWER
M17 A11 E2 K2 K3 J4 L1 R1 VSIM SIM DIO SIM RST
VBUCK (VCC + 1,875V) (VCC + 2.775V) IO_REG VCC_OUT (VCC + 1,8V)
LNA
JSIM
6 2 1
(from PCAP )
LNA
LP Filter
AGC RF Det.
PMA
AAF
(Post Mixer Amplifier) LNA
IF Amp.
100kHz
2 Pole Filter
Dual ADC C9 Analog / Digital A9 Converter B9 D9 D5 C4 B6 A6 D4 TX CP HP-Filter RX Charge Pump
Digital Channal | | BL_V3_A3_BW_L3_8488386N04_B_41.pdf | | V3_ 8488386N04_B_41
Service Engineering & Optimization Level 3 Board Layout
V3 Alexander Buehler, Michael Hansen
REVISIONS
2004.07.08 Rev. 1.0 8488386N04_B_41 Page 1 of 2
V3_ 8488386N04_B_41
Service Engineering & Optimization Level 3 Board Layout
V3 Alexander Buehler, Michael Hansen
REVISIONS
2004.07.08 Rev. 1.0 8488386N04_B_41 Page 2 of 2
| | SCH_V3_A2_C_L3_8488386N04_B_41.pdf | | IO_REG
IO_REG
BATTERY
3 4 PIN3 PIN4 PIN1 PIN2 1 2
SIM BLOCK
SIM_CLK
0687765N01
JTAG TESTPOINTS
RESETB TDO TDI
HS_INT
U1401 R7616
47K
0662057N15
SIDE 1
R1201
100
J_BATT
C1425DNP
ground
KEYBOARD CONNECTOR
J_KEYBRD
0989851N02
3989906N01
VR1205
C1427DNP D1426
0662057M50
TDI
TDO
E_SIM_RST
BP
ground
RESETB
RST
CLK
VSIM_1
IO_REG
4809788E17
1 2 3
TMS
TCK
VSIM
DSP_DEB
SIM_RST
ground
G4 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
G3 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 G1
0989851N02
C1409DNP
R1200
4.7K
0662057M90
J_SIM
CONTACT
VR1204
0687765N01
RESET_OUT_2_7V BB_SPI_MISO BB_SPI_MOSI BB_SPI_CLK BB_SPI_CS6 GA_INT LCD_SDATA LCD_RS LCD_DATA3 LCD_DATA5
C1 A1 C3 A3
RTC_BATT
ground
TCK
TMS
VSIM_2
BP RTC_BATT ATI_CAM_IO
ground
C909 1.0uF
2187893N01
OWB
I_O
3989888N01
BATTP
MCU_DEB
DSP_DEB
GND
RTCK
TRST
THERM
6 5 4
ground
ATI_CAM_IO
C1408DNP R1401
RTCK
TRST
R1202
100
0662057M50
SIM_DIO
E |
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