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File name Gilmor Sammit laptop schematic diagram (Silverthone-Poulsbo Mobile platform).pdf

5 4 3 2 1 D Page 1 2 3 4 5 6 7 Contents COVER PAGE Block diagram Power Sequence Silverthorne CPU-1 Silverthorne CPU-2 Poulsbo-1 Host Bus Poulsbo-2 RTC/LPC/PCIE/LVDS Poulsbo-3 USB/AudioIDE/GPIO Poulsbo-4 DDR2 Poulsbo-5 Chipset Power1 Poulsbo-6 Decoupling Cap Poulsbo-7 Chipset Power2 Poulsbo-8 Chipset VSS DDR2 SODIMM CPU Decoupling Clock CK540 FWH_PIC16F505_PCIE Page 18 19 20 21 22 23 24 Contents USB Ports CF_Thermal sensor C 8 9 10 11 12 13 14 15 B 16 17 A Embedded Menlow XL Processor for Gilmore Summit Baseboard 5 w w w la . 4 to p -s p h c m e 25 26 27 28 29 30 31 32 33 34 ic t a SATA HDD SDIO_TPM1.2 HDMI CH7315B LVDS_HDMI Connector LPC super I/O GPIO header COM1~2_LPC Debug Port HD COEDC ALC262 Audio_Amp C .c s m o D KB/MS_AMP2_RJ22 Ethernet_RTL8111B LAN SWITCH RTL8366SB RJ-45_LAN LED POWER IN +12V, 5VSB VCC, 5V_Dual, 3VSB & VCC3 +2.5VDD,+1.8V,+1.5V,VTT_DDR Vcore B A Title Size Custom Date: Document Number Intel COVER PAGE Gilmore Summit Tuesday, December 30, 2008 Sheet 1 Rev Z000 1 of 35 3 2 5 4 3 2 1 Block Diagram D ISL6262-IMVP6 Vcore P34 Silverthone XL P04,P05 CK540 P16 SDVO HD CODEC 2 DDR2 SO-DIMM CHANNEL A P14 SATA HDD P20 JM20330 P20 DDR2 CHA 18/24-bits LVDS LVDS P14 C Poulsbo XL PCIEx1(1) bus IDE BUS 2.5V, 1.8V, 1.5V, VTT_DDR P33 CF CONN P19 VCC, 5V_Dual, 3VSB & VCC3 P32 USB PORT x 4 Rear Panel USB PORT x 1 (DECT module) USB 0~3 P18 USB 5 USB 6 USB 7 P18 P18 USB PORT x 1 B POWER IN +12V, 5VSB (for Touch screen) P31 USB PORT x 1 (Reserved) P18 LPC BUS TPM P21 4 Bit GPIO DC Jack +12V@4A P31 Power LED A BIOS P17 LPC Debug port P25 Debug LED HDD LED LED Tower 5 w w w la . 4 GPIO_SwitchHook to p P25 W83627DHG P24 -s p P.06~P13 P26 h c P21 PCIEx1(2) bus m e P21 Gbe NIC RTL8111B PCI Express X1 P17 ic t a P23 P28 .c s SDVO-HDMI CH7315B SWITCH DDR2 TERMINATOR m o V1.3 D CPU BUS HDMI P23 P22 RJ-45 RTL8366S P29 P30 C RJ-45 P30 MUTE_MIC GP60 Int_Mic,Int_SP Audio Jack 1~2 (Ext_Mic,Ext_SP) HD CODEC 1 ALC262 B P27 Audio Jack 3 (Headset-out,Headset-in) RJ22 Headset Amp1 SDIO 2 P27 Amp2 P26 SDIO 1 D/A1 HW MONITOR P19 P21 D/A2 P26 Title Size B Date: Document Number A RS232 x 2 KB/MS Intel Block diagram Gilmore Summit Tuesday, December 30, 2008 Sheet 1 Rev Z000 2 of 35 3 2 5 4 3 2 1 POWER SEQUENCE D Poulsbo +1.8V VCCP +1.5V +2.5VDD VTT_DDR PG.33 SYSTEM_PG H_PWRGD 6 Silverthone PG.4-5 PG.6-13 IMVP6_PGOOD 1 Vmonitor VRM_ON 2 PG.17 DELAY 99 ms PG.34 IMVP_ON 3 ISL6262 VCC C VCC3 ISL6545 +12V PG.31 PG.32 PG.32 5VSB PG.31 W83627DHG SIO_PWROK VIN ISL6545 DC IN PG.31 3VSB PG.32 B VIN 5VSB +12V VCC VCC3 +V1.8 A +V0.9SB +1.5V VCCP VCC_CORE 5 w w w la . 4 to p -s p PG.24 h c 5 m e CK540 4 PG.34 PG.16 VR_PWRGD_CLKEN# ic t a 7 5 .c s m o D C 4 DELAY SCH_PWROK PG.32 B A Title Size Custom Date: 3 2 Intel Power sequence Document Number Gilmor