Yideo/Sound Timing Gate Array: VIG
The VTG implements the horizontal and power supply sync signals, the
sound clock, the system timer and the interfaces for the front desk bus
modem and the clock chip.
The horizontal and power supply sync signals are derived from the
video dot rate clock divided by 32 (ie. 2.1888 MHz) using a six bit counter
and write registers 10 thru 13 which provide control of the horizontal
period, horizontal blank stop, horizontal sync start and horizontal sync
stop. The default at reset provides a horizontal rate of 1!l.75KHz and a
power supply sync at twice the horizo~tal period at 99.5KHz.
The refresh/sound counter is fixed at four times the sound rate using a
divide of 41.5 from the 3.6864 Mhz clock which yields a clock of 88.8 KHz.
The system timer is a, 16 bit counter which counts at a rate of one
fourth of the 3.6864 Mhz clock (ie. approximately once every microsecond|