| File information: | |
| File name: | Power Sequence (DC).pdf [preview Power Sequence (DC)] |
| Size: | 13 kB |
| Extension: | |
| Mfg: | HP |
| Model: | Power Sequence (DC) 🔎 |
| Original: | Power Sequence (DC) 🔎 |
| Descr: | HP Power Sequence (DC).pdf |
| Group: | Electronics > Other |
| Uploaded: | 21-01-2020 |
| User: | Anonymous |
| Multipart: | No multipart |
| Information about the files in archive: | ||
| Decompress result: | OK | |
| Extracted files: | 1 | |
File name Power Sequence (DC).pdf 5 4 3 2 1 ON/OFF# PWRBTN t1 -->EC EC-->SB ON/OFFBTN# t2 t3 EC-->SB RSMRST# SB-->EC SLP_S5# D D +1.8V SB-->EC SLP_S4# t4 SB-->EC SLP_S3# t5 +2.5VSP /+3VS /+5VS /+1.5VSP /+1.05V_VCCP /+0.9VSP POK circuit -->EC PWR_GD EC-->NB +VDD_CORE(VCORE) EC-->Power VGATE_INTEL(VRMPWRGD) t6 EC-->SB PM_POK(PWROK) t7 C C H_PWRGOOD(VRMPWRGD AND PWROK) Description Item Min Typical Max Note User press power button t1 --- --- --- User Define User Press power bottun to ICH PWRBTN# t2 --- --- --- HW delay--> 100K & 1uF B B ICH7-M internal de-bounce t3 --- 16ms --- SLP_S4# active to SLP_S5# active t4 1 RTCCLK 2 RTCCLK RTCCLK = 32us SLP_S3# active to SLP_S4# active t5 1 RTCCLK 2 RTCCLK RTCCLK = 32us SLP_S3# active to VRMPWRGD inactive t6 0ms --- --- SLP_S3# active to PWROK inactive t7 0ms --- --- A A 5 4 3 2 1 | ||

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