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Accelerate Design Verification by Characterizing Clock Jitter Using Phase Noise Measurements White Paper Introduction Clock jitter analysis has become more necessary as data rates have increased. In high-speed serial data links clock jitter affects data jitter at the transmitter, in the transmission line, and at the receiver. Measurements of clock quality assurance have also evolved; now the emphasis is on directly relating clock performance to system performance in terms of the bit error ratio (BER). This white paper reviews the role of the reference clock, the effect of clock jitter on data jitter, and discusses a new measurement technique using the Agilent E5001A precision clock jitter analysis application on the E5052B signal source analyzer (SSA). This new method of measurement delivers unprecedented measurement accuracy for ultra-low random jitter (RJ) measurements and real-time jitter spectrum analysis on both the RJ and periodic jitter (PJ) of components, enabling you to improve your design quality. A real-time measurement capability of the new solution that speeds up your design verification process is also discussed. The role of reference Figure 1 shows the major components of a high-speed serial data link. The transmitter usually serializes a set of lower rate parallel signals into a serial clocks in high-speed data stream. The transmission channel through which the signal propagates is serial applications a combination of backplanes and cables. The receiver interprets incoming serial data, re-clocks it and, usually, de-serializes it back into a parallel data stream. In many high-speed serial communication systems, the reference clock is considered more of a constituent than a key player, but in high-speed serial data systems where system bit-rate can be in the multi-gigabit range, the reference clock becomes a key component. Typically the reference clock oscillates at a rate much lower than the data rate and is multiplied up in the transmitter. The transmitter uses the reference clock to define the timing of logic transitions in the serial data stream. The character of the reference clock is included in the data transmitted. At the receiver, two different things can happen. If the reference clock is not distributed, then the receiver recovers a clock from the data stream