Western Digital 03 WD16C550 free download

File name 03_WD16C550.pdf

SYSTEMS LOGIC/PERIPHERAL WD16C550 Enhanced Asynchronous Communications Element (ACE) with FlFOs aee WESTERN DIGITAL WD16C550 TABLE OF CONTENTS Section Title Page 1.0 INTRODUCTION 3-1 1.1 Description 3-1 1.2 Features 3-1 1.1 General 3-2 2.0 CHIP SELECTION AND REGISTER ADDRESSING 3-4 2.1 Address Strobe (ADS) . . . 3-4 2.2 Chip Select (CSO, CS1, CS2) 3-4 2.3 Register Select (AO, A 1, A2) 3-4 3.0 ACE OPERATIONAL DESCRIPTION 3-5 3.1 Master Reset ... 3-5 3.2 ACE Accessible Registers 3-5 3.3 Line Control Register 3-8 3.4 ACE Programmable Baud Rate Generator 3-8 3.5 Line Status Register . . . . 3-11 3.6 Interrupt Identification Register 3-12 3.7 Interrupt Enable Register 3-14 3.8 Scratch Pad Register 3-14 3.9 FIFO Control Register . 3-14 4.0 MODEM CONTROL REGISTER 3-15 5.0 MODEM STATUS REGISTER 3-16 6.0 TYPICAL APPLICATIONS . 3-17 7.0 CRYSTAL MANUFACTURERS (Partial List) 3-18 APPENDICES Section Title Page A.O Pin Designations 3-20 B.O DC Operating Characteristics 3-25 C.O AC Operating Characteristics and Timing Diagrams 3-27 0.0 Package Diagrams . . . . . . . . . . . . . 3-37 12/1/90 3-i WD16C550 LIST OF TABLES Table Title Page 2-1 Register Addressing ... 3-4 3-1 Reset Control of Registers . . . 3-5 3-2 Accessible WD16C550 Registers 3-6 3-3 Baud Rates Using 1.8432 MHz Clock 3-9 3-4 Baud Rates Using 3.072 MHz Clock 3-9 3-5 Baud Rates Using 8.0 MHz Clock 3-10 3-6 Interrupt Control