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Now downloading free:Motorola 74HCT573

Motorola 74HCT573 free download

Electronic circuits, electronic components datasheets and schematics

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File name:74hct573.pdf
[preview 74HCT573]
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Mfg:Motorola
Model:74HCT573 🔎
Original:SN74HCT573 🔎
Descr:OCTAL D-TYPE LATCH DIP20 MC74HCT573A
Group:Electronics > Components > Integrated circuits
Uploaded:09-03-2004
User:plamensl
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File name 74hct573.pdf

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs High­Performance Silicon­Gate CMOS The MC74HCT573A is identical in pinout to the LS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High­Speed CMOS inputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold times becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high­impedance state. Thus, data may be latched even when the outputs are not enabled. The HCT573A is identical in function to the HCT373A but has the Data Inputs on the opposite side of the package from the outputs to facilitate PC board layout. The HCT573A is the noninverting version of the HC563A. · · · · · · Output Drive Capability: 15 LSTTL Loads TTL/NMOS­Compatible Input Levels Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 10 µA In Compliance with the Requirements Defined by JEDEC Standard No. 7A · Chip Complexity: 234 FETs or 58.5 Equivalent Gates -- Improved Propagation Delays -- 50% Lower Quiescent Power LOGIC DIAGRAM D0 D1 D2 DATA INPUTS D3 D4 D5 D6 D7 LATCH ENABLE OUTPUT ENABLE 2 3 4 5 6 7 8 9 11 1 PIN 20 = VCC PIN 10 = GND 19 18 17 16 15 14 13 12 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS MC74HCT573A N SUFFIX PLASTIC PACKAGE CASE 738­03 1 20 20 1 DW SUFFIX SOIC PACKAGE CASE 751D­04 DT SUFFIX TSSOP PACKAGE CASE 948E­02 20 1 ORDERING INFORMATION MC74HCTXXXAN Plastic MC74HCTXXXADW SOIC MC74HCTXXXADT TSSOP PIN ASSIGNMENT OUTPUT ENABLE D0 D1 D2 D3 D4 D5 D6 D7 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 LATCH ENABLE FUNCTION TABLE Inputs Output Enable L L L H Units ea ns Latch Enable H H L X D H L X X Output Q H L No Change Z 10/96 © Motorola, Inc. 1996 Î ÎÎÎ Î ÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Design Criteria Value 58.5 1.5 5.0 Internal Gate Count* Internal Gate Propagation Delay Internal Gate Power Dissipation Speed Power Product µW pJ 0.0075 * Equivalent to a two­input NAND gate. 1 X = Don't Care Z = High Impedance REV 7 MC74HCT573A ÎÎÎ Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î ÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î ÎÎÎÎÎÎ

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