|BIGMAC_Pgmrs_Model_8-85.pdf|| Rich Page
Programmers Model for the Big Mac
This document describes the Big Mac hardware from the programmers
view of the machine which includes a description of the address space
maps and a description of each device.
The CPU clock is generated by the clock generator gate array which is
controlled by three signals CSELO, CSEL 1 and M70. These signals are
controlled by dip switches and described by the following table.
\.~ ~ELQ ~EL1 MIQ ~FREQ |