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DISCRETE SEMICONDUCTORS
DATA SHEET
BF998WR
N-channel dual-gate MOS-FET
Product specification 1997 Sep 05
Supersedes data of 1995 Apr 25
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
FEATURES PINNING
High forward transfer admittance PIN SYMBOL DESCRIPTION
Short channel transistor with high forward transfer 1 s, b source
admittance to input capacitance ratio
2 d drain
Low noise gain controlled amplifier up to 1 GHz.
3 g2 gate 2
4 g1 gate 1
APPLICATIONS
VHF and UHF applications with 12 V supply voltage,
such as television tuners and professional
d
communications equipment.
3 4
g
DESCRIPTION 2
g1
Depletion type field-effect transistor in a plastic
microminiature SOT343R package with source and
substrate interconnected. The transistor is protected
against excessive input voltage surges by integrated 2 1
back-to-back diodes between gates and source. s,b
Top view MAM198
CAUTION
Marking code: MB.
The device is supplied in an antistatic package. The
gate-source input must be protected against static
Fig.1 Simplified outline (SOT343R) and symbol.
discharge during transport or handling.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDS drain-source voltage 12 V
ID drain current 30 mA
Ptot total power dissipation 300 mW
Tj operating junction temperature 150 C
yfs forward transfer admittance 24 mS
Cig1-s input capacitance at gate 1 2.1 pF
Crs reverse transfer capacitance f = 1 MHz 25 fF
F noise figure f = 800 MHz 1 dB
1997 Sep 05 2
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage 12 V
ID drain current 30 mA
IG1 gate 1 current 10 mA
IG2 gate 2 current 10 mA
Ptot total power dissipation up to Tamb = 45 C; see Fig.2; note 1 300 mW
Tstg storage temperature 65 +150 C
Tj operating junction temperature +150 C
Note
1. Device mounted on a printed-circuit board.
MLD154
400
handbook, halfpage
Ptot
(mW)
300
200
100
0
0 50 100 150 200
Tamb ( oC)
Fig.2 Power derating curve.
1997 Sep 05 3
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 350 K/W
Rth j-s thermal resistance from junction to soldering point note 2; Ts = 90 C 200 K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 10 mA 6 20 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 10 mA 6 20 V
V(P)G1-S gate 1-source cut-off voltage VG2-S = 4 V; VDS = 8 V; ID = 20 A 2.5 V
V(P)G2-S gate 2-source cut-off voltage VG1-S = 0; VDS = 8 V; ID = 20 A 2 V
IDSS drain-source current VG2-S = 4 V; VDS = 8 V; VG1-S = 0 2 18 mA
IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 5 V 50 nA
IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 5 V 50 nA
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; ID = 10 mA; VDS = 8 V; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
yfs forward transfer admittance pulsed; Tj = 25 C 22 25 mS
Cig1-s input capacitance at gate 1 f = 1 MHz 2.1 2.5 pF
Cig2-s input capacitance at gate 2 f = 1 MHz 1.2 pF
Cos drain-source capacitance f = 1 MHz 1.05 pF
Crs reverse transfer capacitance f = 1 MHz 25 fF
F noise figure f = 200 MHz; GS = 2 mS; BS = BSopt 0.6 dB
f = 800 MHz; GS = 3.3 mS; BS = BSopt 1 dB
1997 Sep 05 4
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
MGC471 MGC470
24 24
3V
V G1 S =
ID V G2 S = 4 V ID 0.4 V
2V
(mA) (mA)
0.3 V
16 1V 16 0.2 V
0.1 V
0V
8 8 -0.1 V
-0.2 V
-0.3 V
0V -0.4 V
-0.5 V
0 0
1 0 1 0 2 4 6 8 10
V G1 S (V)
V DS (V)
VDS = 8 V. VG2-S = 4 V.
Tamb = 25 C. Tamb = 25 C.
Fig.3 Transfer characteristics; typical values. Fig.4 Output characteristics; typical values.
MGC472 MGC473
24 30
y fs 4V
ID max typ (mS)
(mS) 24
3V
2V
16
1V
18
min 12
8
6
0.5 V
V G2 - S = 0 V
0 0
-1600 -1200 -800 -400 0 400 0 4 8 12 16 20
VG1 (mV) I D (mA)
VDS = 8 V; VG2 = 4 V; Tamb = 25 C. VDS = 8 V; Tamb = 25 C.
Fig.5 Drain current as a function of gate 1 voltage; Fig.6 Forward transfer admittance as a function
typical values. of drain current; typical values.
1997 Sep 05 5
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
MGC474 MGC475
30 1.5
y fs V G2 S = 4 V Cos
(mS) (pF)
24 1.4
3V
18 1.3
12 2V 1.2
ID =
12 mA
6 1V 1.1 10 mA
8 mA
0V
0 1.0
-1 0 1 4 6 8 10 12 14
VG1-S (V) VDS(V)
VDS = 8 V; Tamb = 25 C. VG2-S = 4 V; f = 1 MHz; Tamb = 25 C.
Fig.7 Forward transfer admittance as a function Fig.8 Output capacitance as a function of
of gate 1 voltage; typical values. drain-source voltage; typical values.
MGC476 MGC477
2.4 2.4
Cis Cis
(pF)
(pF)
2.2
2.3
2.0
2.2
1.8
2.1
1.6
1.4 2.0
-2.4 -1.6 -0.8 0 0.8 6 4 2 0 -2
VG1-S (mV) VG2-S (V)
VDS = 8 V; VG2-S = 4 V; f = 1 MHz; Tamb = 25 C. VDS = 8 V; VG1-S = 0 V; f = 1 MHz; Tamb = 25 C.
Fig.9 Gate 1 input capacitance as a function of Fig.10 Gate 1 input capacitance as a function of
gate 1-source voltage; typical values. gate 2-source voltage; typical values.
1997 Sep 05 6
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
MGC466 MGC467
10 10 3 10 3
y is y rs rs
(mS) (S) (deg)
b is rs
1 10 2 10 2
y rs
10 1 10 10
g is
10 2 1 1
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 8 V; VG2-S = 4 V. VDS = 8 V; VG2-S = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.11 Input admittance as a function of the Fig.12 Reverse transfer admittance and phase as
frequency; typical values. a function of frequency; typical values.
MGC468 MGC469
10 2 10 2 10
yos
y fs fs (mS) bos
(mS) y fs (deg)
1
10 10
fs
gos
10 1
1 1 10 2
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 8 V; VG2-S = 4 V. VDS = 8 V; VG2-S = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.13 Forward transfer admittance and phase as Fig.14 Output admittance as a function of the
a function of frequency; typical values. frequency; typical values.
1997 Sep 05 7
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
VDD
47 F
1 nF
VAGC 20 H
1 nF 1 nF
1 nF
1.8 50
47 k L2 input
k
1 nF
C1
5.5 pF
50 1 nF
input
360
L1 15 pF 10 pF
140 k
VDD 1 nF
D1 330 D2 330
BB405 k BB405 k
100
k
1 nF 1 nF
V tun V tun
input output MGC481
VDD = 12 V; GS = 2 mS; GL = 0.5 mS.
L1 = 45 nH; 4 turns 0.8 mm copper wire, internal diameter 4 mm.
L2 = 160 nH; 3 turns 0.8 mm copper wire, internal diameter 8 mm.
Tapped at approximately half a turn from the cold side, to adjust GL = 0.5 mS. C1 adjusted for GS = 2 mS.
Fig.15 Gain control testcircuit at f = 200 MHz.
1997 Sep 05 8
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
V DD VAGC VDD
1 nF
140
1 nF
;; ;;
k
270 L4
100 k 1 nF k
L3 1 nF
50
;;
input
L1 1 nF C3 C4
1 nF 0.5-3.5 pF 4-40 pF
1 nF L2
50
input MGC480
C1 C2
2-18 pF 0.5-3.5 pF 1.8 360
k
V DD
VDD = 12 V; GS = 3.3 mS; GL = 1 mS.
L1 = L4 = 200 nH; 11 turns 0.5 mm copper wire, without spacing, internal diameter 3 mm.
L2 = 2 cm, silvered 0.8 mm copper wire, 4 mm above ground plane.
L3 = 2 cm, silvered 0.5 mm copper wire, 4 mm above ground plane.
Fig.16 Gain control test circuit at f = 800 MHz.
MGC479 MGC478
0 0
Gtr Gtr
(dB) (dB)
-10 -10
IDSS=
-20 -20 max
typ
min
-30 -30
-40 IDSS= -40
max
typ
min
-50 -50
0 2 4 6 8 10 0 2 4 6 8 10
VAGC(V) VAGC(V)
VDD = 12 V; f = 200 MHz; Tamb = 25 C. VDD = 12 V; f = 800 MHz; Tamb = 25 C.
Fig.17 Automatic gain control characteristics Fig.18 Automatic gain control characteristics
measured in circuit of Fig.15. measured in circuit of Fig.16.
1997 Sep 05 9
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
PACKAGE OUTLINE
Plastic surface-mounted package; reverse pinning; 4 leads SOT343R
D B E A X
y HE v M A
e
3 4
Q
A
A1
c
2 1
w M B bp b1 Lp
e1
detail X
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.4 0.7 0.25 2.2 1.35 2.2 0.45 0.23
mm 0.1 1.3 1.15 0.2 0.2 0.1
0.8 0.3 0.5 0.10 1.8 1.15 2.0 0.15 0.13
OUTLINE REFERENCES EUROPEAN
ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
97-05-21
SOT343R
06-03-16
1997 Sep 05 10
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
DATA SHEET STATUS
DOCUMENT PRODUCT
DEFINITION
STATUS(1) STATUS(2)
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
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reserves the right to make changes to information
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published in this document, including without limitation
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specifications and product descriptions, at any time and
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1997 Sep 05 11
NXP Semiconductors Product specification
N-channel dual-gate MOS-FET BF998WR
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Quick reference data The Quick reference data is an
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Limiting values Stress above one or more limiting
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values (as defined in the Absolute Maximum Ratings
qualified nor tested in accordance with automotive testing
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or application requirements. NXP Semiconductors accepts
the device. Limiting values are stress ratings only and
no liability for inclusion and/or use of non-automotive
(proper) operation of the device at these or any other
qualified products in automotive equipment or
conditions above those given in the Recommended
applications.
operating conditions section (if present) or the
Characteristics sections of this document is not warranted. In the event that customer uses the product for design-in
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1997 Sep 05 12
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