Text preview for : 74ls113.pdf part of datasheets 74ls113 . Electronic Components Datasheets Various datasheets 74ls113.pdf
Back to : 74ls113.pdf | Home
SN54/74LS113A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These
monolithic dual flip-flops are designed so that when the clock goes HIGH, the
inputs are enabled and data will be accepted. The logic level of the J and K DUAL JK NEGATIVE
inputs may be allowed to change when the clock pulse is HIGH and the EDGE-TRIGGERED FLIP-FLOP
bistable will perform according to the truth table as long as minimum setup
times are observed. Input data is transferred to the outputs on the LOW POWER SCHOTTKY
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX
CERAMIC
CASE 632-08
14
1
Q Q
5(9) 6(8)
N SUFFIX
PLASTIC
CASE 646-06
SET (SD) 14
4(10)
K 1
J
3(11) 2(12)
1(13)
CLOCK (CP) D SUFFIX
SOIC
14
1 CASE 751A-02
ORDERING INFORMATION
MODE SELECT -- TRUTH TABLE SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
INPUTS OUTPUTS SN74LSXXXD SOIC
OPERATING MODE
SD J K Q Q
Set L X X H L
Toggle H h h q q LOGIC SYMBOL
Load "0" (Reset) H l h L H
Load "1" (Set) H h l H L 4 10
Hold H l l q q
H, h = HIGH Voltage Level SD 11 SD
L, I = LOW Voltage Level 3 J Q 5 J Q 9
X = Don't Care
1 CP 13 CP
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition. 2 K Q 6 12 K Q 8
VCC = PIN 14
GND = PIN 7
FAST AND LS TTL DATA
5-1
SN54/74LS113A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54