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HCF4032B
TRIPLE SERIAL ADDER
s
s
s s s
s
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s s
INVERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS FULLY STATIC OPERATION...DC TO 10MHz (Typ.) at VDD = 10V BUFFERED INPUTS AND OUTPUTS SINGLE PHASE CLOCKING QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4032BEY HCF4032BM1 T&R HCF4032M013TR
DESCRIPTION The HCF4032B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4032B consists of three serial adder circuits with common CLOCK and CARRY-RESET inputs. Each adder has two provisions for two serial DATA INPUT signals and an INVERT command signal. When the command signal is a logical "1", the sum is complemented.
Data words enter the adder with the least significant bit first; the sign bit trails. The output is the MOD 2 sum of the input bits plus the carry from the previous bit position. The carry is only added at the positive going clock transition, thus, for spike-free operation the input data transitions should occur as soon as possible after the triggering edge. The CARRY is reset to a logical "0" at the end of each word by applying a logical "1" signal to a CARRY-RESET input one bit position before the application of the first bit of the next word.
PIN CONNECTION
September 2001
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IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 10, 13, 15 11, 12, 14 7, 5, 2 9, 4, 1 3 6 8 16 SYMBOL A1 to A3 B1 to B3 INVERT1 to INVERT3 SUM1 to SUM3 CLOCK CARRY-RES ET VSS VDD NAME AND FUNCTION Data Inputs Data Inputs Invert Command Inputs Data Outputs Clock Input Carry Reset Input Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
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LOGIC DIAGRAM
TIMING CHART
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW °C °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V °C
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DC SPECIFICATIONS
Test Conditions Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/18.5 0.5/4.5 9/1 1.5/18.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) IO VDD (µA) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±10-5 5 ±0.1 7.5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 ±1 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85°C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125°C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
mA
mA µA pF
II CI
any input any input
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 260 120 90 325 175 150 100 50 40 120 50 40 4.5 10 15 Max. 520 240 180 650 350 300 200 100 80 200 80 60 ns Unit
tPHL tPLH Propagation Delay Time (A, B or Inverter Inputs to Sum Outputs) tPHL tPLH Propagation Delay Time (Clock Inputs to Sum Outputs) tTHL tTLH Transition Time
ns
ns
thold
Data Input Hold Time (clock edge to A, B, or reset inputs) Maximum Clock Input Frequency Clock Input Rise or Fall Time
ns
fMAX
2.5 5 7.5
MHz 500 500 500
tr, tf (1)
µs
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C. (1) If more than one unit is cascaded tr should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving state for the estimated capacitive load.
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
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Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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