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6x86 MICROPROCESSOR
Sixth-Generation Superscalar Superpipelined x86-Compatible CPU
®
Advancing the Standards
Electrical Specifications
4.0 4.1
ELECTRICAL SPECIFICATIONS Electrical Connections
4.1.2
Pull-Up/Pull-Down Resistors
This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, DC characteristics, and AC characteristics. All voltage values in Electrical Specifications are measured with respect to VSS unless otherwise noted. 4.1.1 Power and Ground Connections and Decoupling
Table 4-1 lists the input pins that are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted.
Table 4-1. Pins Connected to Internal Pull-Up and Pull-Down Resistors
SIGNAL PIN NO. RESISTOR
Testing and operating the 6x86 CPU requires the use of standard high frequency techniques to reduce parasitic effects. The high clock frequencies used in the 6x86 CPU and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VCC and GND pins. The 6x86 CPU contains 296 pins with 53 pins connected to VCC and 53 connected to VSS (ground).
BRDYC# CLKMUL QDUMP# SMI# SUSP# TCK TDI TMS TRST# Reserved Reserved Reserved Reserved
Y3 Y33 AL7 AB34 Y34 M34 N35 P34 Q33 J33 W35 Y35 AN35
20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up (see text)
20-k pull-up
20-k pull-down
PRELIMINARY
4-1
®
Absolute Maximum Ratings
Advancing the Standards
4.1.3
Unused Input Pins
4.2
Absolute Maximum Ratings
All inputs not used by the system designer and not listed in Table 4-1 should be connected either to ground or to VCC. Connect active-high inputs to ground through a 20 k (± 10%) pull-down resistor and active-low inputs to VCC through a 20 k (± 10%) pull-up resistor to prevent possible spurious operation. 4.1.4 NC and Reserved Pins
Pins designated NC have no internal connections. Pins designated RESV or RESERVED should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions.
The following table lists absolute maximum ratings for the 6x86 CPU microprocessors. Stresses beyond those listed under Table 4-2 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" Table 4-3 (Page 4-3) is possible. Exposure to conditions beyond Table 4-2 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings may also result in reduced useful life and reliability.
Table 4-2. Absolute Maximum Ratings
PARAMETER MIN MAX UNITS NOTES
Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK
-65 -65 -0.5 -0.5
110 150 4.0 VCC +0.5 10 25
°C °C V V mA mA
Power Applied
Power Applied Power Applied
4-2
PRELIMINARY
Recommended Operating Conditions
4
4.3
Recommended Operating Conditions
Table 4-3 presents the recommended operating conditions for the 6x86 CPU device.
Table 4-3. Recommended Operating Conditions
PARAMETER MIN MAX UNITS NOTES
TC Operating Case Temperature VCC Supply Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage IOH High-Level Output Current All outputs except A20-A3 and W/R# A20-A3 and W/R# IOL Low-Level Output Current All outputs except A20-A3 and W/R# A20-A3 and W/R#
0 3.15 2.0 -0.3
70 3.6 5.5 0.8 -1.0 -2.0 5.0 10.0
°C V V V mA
Power Applied
VO=VOH(MIN) VO=VOL(MAX}
mA
PRELIMINARY
4-3
®
DC Characteristics
Advancing the Standards
4.4
DC Characteristics
Table 4-4. DC Characteristics (at Recommended Operating Conditions)
PARAMETER MIN TYP MAX UNITS NOTES
Output Low Voltage IOL = 5 mA VOH Output High Voltage IOH = -1 mA Input Leakage Current II For all pins except those listed in Table 4-1. IIH Input Leakage Current For all pins with internal pull-downs. IIL Input Leakage Current For all pins with internal pull-ups. ICC Active ICC 80 MHz 100 MHz 110 MHz 120 MHz 133 MHz ICCSM Suspend Mode ICC 80 MHz 100 MHz 110 MHz 120 MHz 133 MHz ICCSS Standby ICC 0 MHz (Suspended/CLK Stopped) Input Capacitance CIN COUT Output Capacitance I/O Capacitance CIO CCLK CLK Capacitance
VOL
0.4 2.4 ±15
V V µA
0 < VIN < VCC VIH = 2.4 V See Table 4-1. VIL = 0.45 V See Table 4-1. Note 1, 5
200
µA µA
-400
3.9 4.5 4.8 5.1 5.5 43 48 50 51 54 35
4.7 5.4 5.8 6.1 6.6 75 80 83 86 95 55 15 20 25 15
A
Note 1, 3, 5 mA
mA pF pF pF pF
Note 4,5 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2 f = 1 MHz, Note 2
Notes: 1. Frequency (MHz) ratings refer to the internal clock frequency. 2. Not 100% tested. 3. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded (static IOUT = 0 mA). 4. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static and all outputs unloaded (static IOUT = 0 mA). 5. Typical, measured at VCC = 3.3 V.
4-4
PRELIMINARY
AC Characteristics
4
4.5
AC Characteristics
are shown in Table 4-5. Input or output signals must cross these levels during testing. Figure 4-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation.
Tables 4-6 through 4-11 (Pages 4-7 through 4-13) list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 4-1 (Page 4-6) and Figure 4-2 (Page 4-7). The rising clock edge , reference level VREF and other reference levels
PRELIMINARY
4-5
®
AC Characteristics
Advancing the Standards
Tx VIHD
CLK:
VIL D
VREF
VRE F
A B
OUTPUTS:
Valid VR EF Output n
MAX
MIN
VR EF Valid Output n+1
VIHD
C
VR EF
Valid Input
D
VR EF
INPUTS: VIL D
LEGEND: A - Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold Specification
1709406
Figure 4-1. Drive Level and Measurement Points for Switching Characteristics
Table 4-5. Drive Level and Measurement Points for Switching Characteristics
SYMBOL VOLTAGE (Volts)
VREF VIHD VILD
Note: Refer to Figure 4-1.
1.5 2.3 0
4-6
PRELIMINARY
4
AC Characteristics
Table 4-6. Clock Specifications TCASE = 0°C to 70°C, See Figure 4-2
SYMBOL
PARAMETER
40-MHz BUS 50-MHz BUS MIN MAX MIN MAX
55-MHz BUS MIN MAX
60-MHz BUS MIN MAX
66-MHz BUS MIN MAX
UNITS
T1 T2 T3 T4 T5 T6
CLK Frequency CLK Period 25 CLK Period Stability CLK High Time 9 CLK Low Time 9 CLK Fall Time 0.15 CLK Rise Time 0.15
40 20 ± 250 7 7 0.15 0.15
50 18 ± 250 4.0 4.0 0.15 0.15
55 ±250
2 2
2 2
1.5 1.5
60 16.67 33.33 ±250 4.0 4.0 0.15 1.5 0.15 1.5
15.0 4.0 4.0 0.15 0.15
66.6 30.0 ±250
1.5 1.5
MHz ns ps ns ns ns ns
T1
T3 V IH(MIN) V REF V IL(MAX)
CLK
T6 T4 T5
1740502
Figure 4-2. CLK Timing and Measurement Points
PRELIMINARY
4-7
®
Advancing the Standards
.
Table 4-7. Output Valid Delays , CL = 50 pF Tcase = 0°C to 70°C, See Figure 4-3
PARAMETER 40-MHz BUS 50-MHz BUS 55-MHz BUS 60-MHz BUS 66-MHz BUS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS
T7a A31-A3, BE7#-BE0#, CACHE#, D/C#, LBA#, LOCK#, PCD, PWT, SCYC, SMIACT#, W/R# T7b ADS#, M/IO# T8 ADSC# T9 AP T10 APCHK#, PCHK#, FERR# T11 D63-D0, DP7-DP0 (Write) T12a HIT# T12b HITM# T13 BREQ, HLDA T14 SUSPA#
3
14
1.0
12
1.0
7.0
1.0
7.0
1.0
7.0
ns
3 3 3 3 3 3 3 3 3
14 14 14 16 14 14 14 14 16
1.0 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0
12 12 12 14 12 12 12 12 14
1.0 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0
7.0 7.0 8.5 8.3 8.5 8.0 6.0 8.0 8.0
1.0 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0
7.0 7.0 8.5 7.0 7.5 8.0 6.0 8.0 8.0
1.0 1.0 1.0 1.0 1.3 1.0 1.1 1.0 1.0
6.0 7.0 8.5 7.0 7.5 8.0 6.0 8.0 8.0
ns ns ns ns ns ns ns
Tx CLK
MIN
Tx
Tx
Tx
MAX
T7 - T14 VALID n+1
OUTPUTS
VALID n
1740900
Figure 4-3.
Output Valid Delay Timing
4-8
PRELIMINARY
4
Table 4-8. Output Float Delays , CL = 50 pF Tcase = 0°C to 70°C, See Figure 4-5
PARAMETER 40-MHz BUS 50-MHz BUS 55-MHz BUS 60-MHz BUS 66-MHz BUS MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS
T15 A31-A3, ADS#, BE7#-BE0#, BREQ, CACHE#, D/C#, LBA#, LOCK#, M/IO#, PCD, PWT, SCYC, SMIACT#, W/R# T16 AP T17 D63-D0, DP7-DP0 (Write)
19
16
10.0
10.0
10.0
ns
19 19
16 16
10.0 10.0
10.0 10.0
10.0 10.0
ns ns
Tx CLK
T15 - T17
Tx
Tx
Tx
MIN
MAX
OUTPUTS
VALID
1741000
Figure 4-4. Output Float Delay Timing
PRELIMINARY
4-9
®
Advancing the Standards
Table 4-9. Input Setup Times Tcase = 0°C to 70°C, See Figure 4-5
PARAMETER 40-MHz BUS MIN 50-MHz BUS MIN 55-MHz BUS MIN 60-MHz BUS MIN 66-MHz BUS MIN UNITS
T18 A20M#, FLUSH#, IGNNE#, SUSP# T19 AHOLD, BHOLD, BOFF#, DHOLD, HOLD T20 BRDY# T21 BRDYC# T22 A31-A3, AP, BE7#-BE0#, T22a D63-D0 (Read), DP7-DP0 (Read) T23 EADS#, INV T24 INTR, NMI, RESET, SMI#, WM_RST T25 EWBE#, KEN#, NA#, WB/WT# T26 QDUMP#
5.0 5.0 5.0 5.0 5.0 3.8 5.0 5.0 5.0 5.0
5.0 5.0 5.0 5.0 5.0 3.8 5.0 5.0 5.0 5.0
5.0 5.0 5.0 5.0 5.0 3.8 5.0 5.0 4.5 5.0
5.0 5.0 5.0 5.0 5.0 3.0 5.0 5.0 4.5 5.0
5.0 5.0 5.0 5.0 5.0 3.0 5.0 5.0 4.5 5.0
ns ns ns ns ns ns ns ns ns
Table 4-10. Input Hold Times Tcase = 0°C to 70°C, See Figure 4-5
SYMBOL PARAMETER 40-MHz BUS MIN 50-MHz BUS MIN 55-MHz BUS MIN 60-MHz BUS MIN 66-MHz BUS MIN UNITS
T27 T28 T29 T30 T31a T31b T32 T33 T34 T35
A20M#, FLUSH#, IGNNE#, SUSP# AHOLD, BHOLD, BOFF#, DHOLD, HOLD BRDY# BRDYC# A31-A3, AP BE7#-BE0# , D63-D0, DP7-DP0 (Read) EADS#, INV INTR, NMI, RESET, SMI#, WM_RST EWBE#, KEN#, NA#, WB/WT# QDUMP#
3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0
2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0
1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0
1.0 1.0 1.0 1.0 1.0 2.0 1.0 1.0 1.0 1.0
ns ns ns ns ns ns ns ns ns ns
4-10
PRELIMINARY
4
Tx
Tx
Tx
Tx
CLK T18 - T26 SETUP T27 - T35 HOLD
1740600
Figure 4-5. Input Setup and Hold Timing
PRELIMINARY
4-11
®
Advancing the Standards
Table 4-11. JTAG AC Specifications
SYMBOL PARAMETER ALL BUS FREQUENCIES MIN MAX UNITS FIGURE
T36 T37 T38 T39 T40 T41 T42 T43 T44 T45 T46 T47 T48 T49
TCK Frequency (MHz) TCK Period TCK High Time TCK Low Time TCK Rise Time TCK Fall Time TDO Valid Delay Non-test Outputs Valid Delay TDO Float Delay Non-test Outputs Float Delay TRST# Pulse Width TDI, TMS Setup Time Non-test Inputs Setup Time TDI, TMS Hold Time Non-test Inputs Hold Time
20 50 25 25 5 5 20 20 25 25
3 3
40 20 20 13 13
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4-6 4-6 4-6 4-6 4-6 4-7 4-7 4-7 4-7 4-8 4-7 4-7 4-7 4-7
T36
T37 V IH V REF V IL
TCK
T39
T38
T40
1741102
Figure 4-6. TCK Timing and Measurement Points
4-12
PRELIMINARY
4
TCK
1.5 V T46 T48
TDI TMS
T41 T43
TDO
T42 T44
OUTPUT SIGNALS
T47 T49
INPUT SIGNALS
1740400
Figure 4-7. JTAG Test Timings
T45 TRST#
1.5 V 1741200
Figure 4-8. Test Reset Timing
PRELIMINARY
4-13