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M1-1.PDF1- 6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU Advancing the Standards Introduction Product Overview 1. ARCHITECTURE OVERVIEW The Cyrix 6x86 CPU is a leader in the sixth generation of high performance, x86-compatible processors. Increased performance is accomplished by the use of superscalar and superpipelined design techniques. The 6x86 CPU is superscalar in that it contains two separate pipelines that allow multiple instructions to be processed at the same time. The use of advanced processing technology and the increased number of pipeline stages (superpipelining) allow the 6x86 CPU to achieve clocks rates of 100 MHz and above. Through the use of unique architectural features, the 6x86 processor eliminates many data dependencies and resource conflicts, resulting in optimal performance for both 16-bit and 32-bit x86 software. The 6x86 CPU contains two caches: a 16-KByte dual-ported unified cache and a 256-byte instruction line cache. Since t
M1-2.pdf6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU Advancing the Standards Programming Interface 2. PROGRAMMING INTERFACE 2.1 Processor Initialization In this chapter, the internal operations of the 6x86 CPU are described mainly from an application programmer's point of view. Included in this chapter are descriptions of processor initialization, the register set, memory addressing, various types of interrupts and the shutdown and halt process. An overview of real, virtual 8086, and protected operating modes is also included in this chapter. The FPU operations are described separately at the end of the chapter. This manual does not--and is not intended to--describe the 6x86 microprocessor or its operations at the circuit level. The 6x86 CPU is initialized when the RESET signal is asserted. The processor is placed in real mode and the registers listed in Table 2-1 (Page 2-2) are set to their initialized values. RESET invalidates and disables the cac
M1-3.pdf6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU Advancing the Standards Bus Interface 3.0 6x86 BUS INTERFACE The signals used in the 6x86 CPU bus interface are described in this chapter. Figure 3-1 shows the signal directions and the major signal groupings. A description of each signal and their reference to the text are provided in Table 3-1 (Page 3-2). INTR Clock Control Reset CLK CLKMUL RESET WM_RST NMI SMI# EWBE# FLUSH# KEN# A31 - A3 PCD PWT BE7# - BE0# A20M# Interrupt Control Cache Control Address Bus WB/WT# BOFF# BREQ HOLD HLDA Address Parity Data Bus AP APCHK# D63 - D0 Bus Arbitration AHOLD Data Parity DP7 - DP0 PCHK# 6x86 CPU EADS# HIT# HITM# INV Cache Coherency CACHE# D/C# FERR# IGNNE# BHOLD FPU Error Bus Cycle Definition LOCK# M/IO# DHOLD LBA# QDUMP# SUSP# SCYC W/R# Scatter Gather Buffer ADS# ADSC# Bus Cycle Control BRDY# BRDYC# NA# SUSPA# TCK TDI TDO TMS TRST# Power Management JTAG SMIACT# 1 7 37 9 00 Figur
M1-4.pdf6x86 MICROPROCESSOR Sixth-Generation Superscalar Superpipelined x86-Compatible CPU Advancing the Standards Electrical Specifications 4.0 4.1 ELECTRICAL SPECIFICATIONS Electrical Connections 4.1.2 Pull-Up/Pull-Down Resistors This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, DC characteristics, and AC characteristics. All voltage values in Electrical Specifications are measured with respect to VSS unless otherwise noted. 4.1.1 Power and Ground Connections and Decoupling Table 4-1 lists the input pins that are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. Table 4-1. Pins Connected to Internal Pull-Up and Pull-Dow
M1-5.pdf6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU Advancing the Standards Mechanical Specifications 5.0 5.1 MECHANICAL SPECIFICATIONS 296-Pin SPGA Package The pin assignments for the 6x86 CPUin a 296-pin SPGA package are shown in Figure 5-1. The pins are listed by signal name in Table 5-1(Page 5-2) and by pin number in Table 5-2 (Page 5-3). Dimensions are shown in Figure 5-2 (Page 5-4) and Table 5-3 (Page 5-5). 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG VSS A30 VSS A28 VSS RESV A4 A3 A29 A25 A6 A8 A7 A5 A31 A10 VSS A11 A9 VCC VSS A12 A13 VCC VSS A14 A15 VCC VSS A16 A17 VCC VSS A18 A19 VCC VSS A20 VCC VSS RESV CLK VCC VSS SCYC VCC VSS BE6# VCC VSS BE4# VCC VSS BE2# VCC FLUSH# VSS W/R# NC EADS# NC ADSC# NC AN AM AL BE0# QDUMP# HITM# HIT# D/C# PWT AP NC RESET BE7# BE5# BE3# BE1# A20M# AK BREQ ADS# HLDA AJ AH AG A22 VCC VSS VCC NC A24 A26
M1-6.pdf6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU Advancing the Standards Instruction Set 6. INSTRUCTION SET 6.1 Instruction Set Summary This section summarizes the 6x86 CPU instruction set and provides detailed information on the instruction encodings. All instructions are listed in the CPU Instruction Set Summary Table (Table 6-20, Page 6-14), and the FPU Instruction Set Summary Table (Table 6-22, Page 6-30). These tables provide information on the instruction encoding, and the instruction clock counts for each instruction. The clock count values for both tables are based on the assumptions described in Section 6.3. Depending on the instruction, the 6x86 CPU instructions follow the general instruction format shown in Figure 6-1. These instructions vary in length and can start at any byte address. An instruction consists of one or more bytes that can include: prefix byte(s), at least one opcode byte(s), mod r/m byte, s-i-b byte, address displace

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