Text preview for : M1-6.pdf part of Cyrix 6x86 Cyrix 6x86 Datasheet
Back to : CYRIX.zip | Home
6x86 PROCESSOR
Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU
®
Advancing the Standards
Instruction Set
6.
INSTRUCTION SET
6.1
Instruction Set Summary
This section summarizes the 6x86 CPU instruction set and provides detailed information on the instruction encodings. All instructions are listed in the CPU Instruction Set Summary Table (Table 6-20, Page 6-14), and the FPU Instruction Set Summary Table (Table 6-22, Page 6-30). These tables provide information on the instruction encoding, and the instruction clock counts for each instruction. The clock count values for both tables are based on the assumptions described in Section 6.3.
Depending on the instruction, the 6x86 CPU instructions follow the general instruction format shown in Figure 6-1. These instructions vary in length and can start at any byte address. An instruction consists of one or more bytes that can include: prefix byte(s), at least one opcode byte(s), mod r/m byte, s-i-b byte, address displacement byte(s) and immediate data byte(s). An instruction can be as short as one byte and as long as 15 bytes. If there are more than 15 bytes in the instruction a general protection fault (error code of 0) is generated.
P P P P P P P P T T T T T T T T mod 0 76 7 0 7 optional prefix byte(s) op-code (one or two bytes)
R R R r/m ss 543 210 76
mod r/m byte
index 543 s-i-b byte
base 21 0
32
16
8
none
32
16
8 none
P = prefix bit T = opcode bit R = opcode bit or reg bit
address displacement (4, 2, 1 bytes, or none)
immediate data (4, 2, 1 bytes, or none)
1703103
register and address mode specifier
Figure 6-1.
Instruction Set Format
PRELIMINARY
6-1
®
Instruction Set Summary
Advancing the Standards
6.2
General Instruction Fields
The fields in the general instruction format at the byte level are listed in Table 6-1.
Table 6-1. Instruction Fields
FIELD NAME DESCRIPTION WIDTH
Optional Prefix Byte(s) Specifies segment register override, address and operand size, repeat elements in string instruction, LOCK# assertion. Opcode Byte(s) Identifies instruction operation. mod and r/m Byte Address mode specifier. s-i-b Byte Scale factor, Index and Base fields. Address Displacement Address displacement operand. Immediate data Immediate data operand.
1 or more bytes 1 or 2 bytes 1 byte 1 byte 1, 2 or 4 bytes 1, 2 or 4 bytes
6.2.1
Optional Prefix Bytes
Prefix bytes can be placed in front of any instruction. The prefix modifies the operation of the next instruction only. When more than one prefix is used, the order is not important. There are five type of prefixes as follows: 1. 2. 3. 4. 5. Segment Override explicitly specifies which segment register an instruction will use for effective address calculation. Address Size switches between 16- and 32-bit addressing. Selects the inverse of the default. Operand Size switches between 16- and 32-bit operand size. Selects the inverse of the default. Repeat is used with a string instruction which causes the instruction to be repeated for each element of the string. Lock is used to assert the hardware LOCK# signal during execution of the instruction.
6-2
PRELIMINARY
Instruction Set Summary
6
Table 6-2 lists the encodings for each of the available prefix bytes.
Table 6-2. Instruction Prefix Summary
PREFIX ENCODING DESCRIPTION
ES: CS: SS: DS: FS: GS: Operand Size Address Size LOCK REPNE REP/REPE
26h 2Eh 36h 3Eh 64h 65h 66h 67h F0h F2h F3h
Override segment default, use ES for memory operand Override segment default, use CS for memory operand Override segment default, use SS for memory operand Override segment default, use DS for memory operand Override segment default, use FS for memory operand Override segment default, use GS for memory operand Make operand size attribute the inverse of the default Make address size attribute the inverse of the default Assert LOCK# hardware signal. Repeat the following string instruction. Repeat the following string instruction.
PRELIMINARY
6-3
®
Instruction Set Summary
Advancing the Standards
6.2.2
Opcode Byte
The opcode field specifies the operation to be performed by the instruction. The opcode field is either one or two bytes in length and may be further defined by additional bits in the mod r/m byte. Some operations have more than one opcode, each specifying a different form of the operation. Some opcodes name instruction groups. For example, opcode 80h names a group of operations that have an immediate operand and a register or memory operand. The reg field may appear in the second opcode byte or in the mod r/m byte. 6.2.2.1 w Field
The 1-bit w field (Table 6-11) selects the operand size during 16 and 32 bit data operations.
Table 6-3. w Field Encoding
w FIELD OPERAND SIZE 16-BIT DATA OPERATIONS 32-BIT DATA OPERATIONS
0 1
8 Bits 16 Bits
8 Bits 32 Bits
6.2.2.2
d Field
The d field (Table 6-4) determines which operand is taken as the source operand and which operand is taken as the destination.
Table 6-4. d Field Encoding
d FIELD DIRECTION OF OPERATON SOURCE OPERAND DESTINATION OPERAND
0 1
Register --> Register or Register --> Memory Register --> Register or Memory --> Register
reg mod r/m or mod ss-index-base
mod r/m or mod ss-index-base reg
6-4
PRELIMINARY
Instruction Set Summary
6
6.2.2.3
s Field
The s field (Table 6-5) determines the size of the immediate data field. If the S bit is set, the immediate field of the OP code is 8-bits wide and is sign extened to match the operand size of the opcode.
Table 6-5. s Field Encoding
s FIELD Immediate Field Size 8-Bit Operand Size 16-Bit Operand Size 32-Bit Operand Size
0 (or not present) 1
8 bits 8 bits
16 bits 8 bits (sign extended)
32 bits 8 bits (sign extended)
6.2.2.4
eee Field
The eee field (Table 6-6) is used to select the control, debug and test registers in the MOV instructions. The type of register and base registers selected by the eee field are listed in Table 6-6. The values shown in Table 6-6 are the only valid encodings for the eee bits.
Table 6-6. eee Field Encoding
eee FILED REGISTER TYPE BASE REGISTER
000 010 011 000 001 010 011 110 111 011 100 101 110 111
Control Register Control Register Control Register Debug Register Debug Register Debug Register Debug Register Debug Register Debug Register Test Register Test Register Test Register Test Register Test Register
CR0 CR2 CR3 DR0 DR1 DR2 DR3 DR6 DR7 TR3 TR4 TR5 TR6 TR7
PRELIMINARY
6-5
®
Instruction Set Summary
Advancing the Standards
6.2.3
mod and r/m Byte
The mod and r/m fields (Table 6-7), within the mod r/m byte, select the type of memory addressing to be used. Some instructions use a fixed addressing mode (e.g., PUSH or POP) and therefore, these fields are not present. Table 6-7 lists the addressing method when 16-bit addressing is used and a mod r/m byte is present. Some mod r/m field encodings are dependent on the w field and are shown in Table 6-8 (Page 6-7).
Table 6-7. mod r/m Field Encoding
mod and r/m fields 16-BIT ADDRESS MODE with mod r/m Byte 32-BIT ADDRESS MODE with mod r/m Byte and No s-i-b Byte Present
00 000 00 001 00 010 00 011 00 100 00 101 00 110 00 111 01 000 01 001 01 010 01 011 01 100 01 101 01 110 01 111 10 000 10 001 10 010 10 011 10 100 10 101 10 110 10 111 11 000-11 111
DS:[BX+SI] DS:[BX+DI] DS:[BP+SI] DS:[BP+DI] DS:[SI] DS:[DI] DS:[d16] DS:[BX] DS:[BX+SI+d8] DS:[BX+DI+d8] DS:[BP+SI+d8] DS:[BP+DI+d8] DS:[SI+d8] DS:[DI+d8] SS:[BP+d8] DS:[BX+d8] DS:[BX+SI+d16] DS:[BX+DI+d16] DS:[BP+SI+d16] DS:[BP+DI+d16] DS:[SI+d16] DS:[DI+d16] SS:[BP+d16] DS:[BX+d16] See Table 6-7
DS:[EAX] DS:[ECX] DS:[EDX] DS:[EBX] s-i-b is present (See 6.2.4 (Page 6-9)) DS:[d32] DS:[ESI] DS:[EDI] DS:[EAX+d8] DS:[ECX+d8] DS:[EDX+d8] DS:[EBX+d8] s-i-b is present (See 6.2.4 (Page 6-9)) SS:[EBP+d8] DS:[ESI+d8] DS:[EDI+d8] DS:[EAX+d32] DS:[ECX+d32] DS:[EDX+d32] DS:[EBX+d32] s-i-b is present (See 6.2.4 (Page 6-9)) SS:[EBP+d32] DS:[ESI+d32] DS:[EDI+d32] See Table 6-7
6-6
PRELIMINARY
Instruction Set Summary
6
Table 6-8. mod r/m Field Encoding Dependent on w Field
mod r/m 16-BIT OPERATION w = 0 16-BIT OPERATION w = 1 32-BIT OPERATION w = 0 32-BIT OPERATION w = 1
11 000 11 001 11 010 11 011 11 100 11 101 11 110 11 111
AL CL DL BL AH CH DH BH
AX CX DX BX SP BP SI DI
AL CL DL BL AH CH DH BH
EAX ECX EDX EBX ESP EBP ESI EDI
6.2.3.1
reg Field
The reg field (Table 6-9) determines which general registers are to be used. The selected register is dependent on whether a 16 or 32 bit operation is current and the status of the w bit.
Table 6-9. reg Field
reg 16-BIT OPERATION w Field Not Present 32-BIT OPERATION w Field Not Present 16-BIT OPERATION w = 0 16-BIT OPERATION w = 1 32-BIT OPERATION w = 0 32-BIT OPERATION w = 1
000 001 010 011 100 101 110 111
AX CX DX BX SP BP SI DI
EAX ECX EDX EBX ESP EBP ESI EDI
AL CL DL BL AH CH DH BH
AX CX DX BX SP BP SI DI
AL CL DL BL AH CH DH BH
EAX ECX EDX EBX ESP EBP ESI EDI
PRELIMINARY
6-7
®
Instruction Set Summary
Advancing the Standards
6.2.3.2
sreg3 Field
The sreg3 field (Table 6-10) is 3-bit field that is similar to the sreg2 field, but allows use of the FS and GS segment registers.
Table 6-10. sreg3 Field Encoding
sreg3 FIELD SEGMENT REGISTER SELECTED
000 001 010 011 100 101 110 111
ES CS SS DS FS GS undefined undefined
6.2.3.3
sreg2 Field
The sreg2 field (Table 6-11) is a 2-bit field that allows one of the four 286-type segment registers to be specified.
Table 6-11. sreg2 Field Encoding
sreg2 FIELD SEGMENT REGISTER SELECTED
00 01 10 11
ES CS SS DS
6-8
PRELIMINARY
Instruction Set Summary
6
6.2.4
s-i-b Byte
The s-i-b fields provide scale factor, indexing and a base field for address selection. 6.2.4.1 ss Field
The ss field (Table 6-12) specifies the scale factor used in the offset mechanism for address calculation. The scale factor multiplies the index value to provide one of the components used to calculate the offset address.
Table 6-12. ss Field Encoding
ss FIELD SCALE FACTOR
00 01 01 11
x1 x2 x4 x8
6.2.4.2
index Field
The index field (Table 6-13) specifies the index register used by the offset mechanism for offset address calculation. When no index register is used (index field = 100), the ss value must be 00 or the effective address is undefined.
Table 6-13. index Field Encoding
Index FIELD INDEX REGISTER
000 001 010 011 100 101 110 111
EAX ECX EDX EBX none EBP ESI EDI
PRELIMINARY
6-9
®
Instruction Set Summary
Advancing the Standards
6.2.4.3
Base Field
In Table 6-7 (Page 6-6), the note "s-i-b present" for certain entries forces the use of the mod and base field as listed in Table 6-14. The first two digits in the first column of Table 6-14 identifies the mod bits in the mod r/m byte. The last three digits in the first column of this table identifies the base fields in the s-i-b byte.
Table 6-14. mod base Field Encoding
mod FIELD WITHIN mode/rm BYTE base FIELD WITHIN s-i-b BYTE 32-BIT ADDRESS MODE with mod r/m and s-i-b Bytes Present
00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10
000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111
DS:[EAX+(scaled index)] DS:[ECX+(scaled index)] DS:[EDX+(scaled index)] DS:[EBX+(scaled index)] SS:[ESP+(scaled index)] DS:[d32+(scaled index)] DS:[ESI+(scaled index)] DS:[EDI+(scaled index)] DS:[EAX+(scaled index)+d8] DS:[ECX+(scaled index)+d8] DS:[EDX+(scaled index)+d8] DS:[EBX+(scaled index)+d8] SS:[ESP+(scaled index)+d8] SS:[EBP+(scaled index)+d8] DS:[ESI+(scaled index)+d8] DS:[EDI+(scaled index)+d8] DS:[EAX+(scaled index)+d32] DS:[ECX+(scaled index)+d32] DS:[EDX+(scaled index)+d32] DS:[EBX+(scaled index)+d32] SS:[ESP+(scaled index)+d32] SS:[EBP+(scaled index)+d32] DS:[ESI+(scaled index)+d32] DS:[EDI+(scaled index)+d32]
6-10
PRELIMINARY
CPUID Instruction
6
6.3
CPUID Instruction
The 6x86 CPU executes the CPUID instruction (opcode 0FA2) as documented in this section only if the CPUID bit in the CCR4 configuration register is set. The CPUID instruction may be used by software to determine the vendor and type of CPU. When the CPUID instruction is executed with EAX = 0, the ASCII characters "CyrixInstead" are placed in the EBX, EDX, and ECX registers as shown in Table 6-15:
When the CPUID instruction is executed with EAX = 1, EAX and EDX contain the values shown in Table 6-16.
Table 6-16. CPUID Data Returned When EAX = 1
REGISTER CONTENTS
EAX(3-0) EAX(7-4) EAX(11-8) EAX(13-12) EAX(31-14) EDX
Table 6-15. CPUID Data Returned When EAX = 0
REGISTER CONTENTS (D31 - D0)
0 3 5 0 reserved If EDX = 00, FPU not on-chip. If EDX = 01, FPU on-chip.
EBX EDX ECX *ASCII equivalent
69 72 79 43
i s d r n a y I e C* x* t*
73 6E 49 78 64 61 65 74
PRELIMINARY
6-11
®
Instruction Set Tables
Advancing the Standards
6.4
Instruction Set Tables
The 6x86 CPU instruction set is presented in two tables: Table 6-20. "6x86 CPU Instruction Set Clock Count Summary" on page 6-14 and Table 6-22. "6x86 FPU Instruction Set Summary" on page 6-30. Additional information concerning the FPU Instruction Set is presented on page 6-29. 6.4.1 Assumptions Made in Determining Instruction Clock Count
However, if the effective address calculation uses two general register components, add 1 clock to the clock count shown. 7. 8. All clock counts assume aligned 32-bit memory/ IO operands. If instructions access a 32-bit operand that crosses a 64-bit boundary, add 1 clock for read or write and add 2 clocks for read and write. For non-cached memory accesses, add two clocks (6x86 CPU with 2x clock) or four clocks (6x86 CPU with 3x clock). (Assumes zero wait state memory accesses).
The assumptions made in determining instruction clock counts are listed below: 1. All clock counts refer to the internal CPU internal clock frequency. For example, the clock counts for a clock-doubled 6x86 CPU-100 refer to 100 MHz clocks while the external clock is 50 MHz. The instruction has been prefetched, decoded and is ready for execution. Bus cycles do not require wait states. There are no local bus HOLD requests delaying processor access to the bus. No exceptions are detected during instruction execution. If an effective address is calculated, it does not use two general register components. One register, scaling and displacement can be used within the clock count shown.
9.
2.
10. Locked cycles are not cacheable. Therefore, using the LOCK prefix with an instruction adds additional clocks as specified in paragraph 9 above. 11. No parallel execution of instructions. 6.4.2 CPU Instruction Set Summary Table Abbreviations
3. 4.
5. 6.
The clock counts listed in the CPU Instruction Set Summary Table are grouped by operating mode and whether there is a register/cache hit or a cache miss. In some cases, more than one clock count is shown in a column for a given instruction, or a variable is used in the clock count. The abbreviations used for these conditions are listed in Table 6-17.
6-12
PRELIMINARY
Instruction Set Tables
6
Table 6-17. CPU Clock Count Abbreviations
CLOCK COUNT SYMBOL EXPLANATION
/ n L | \ m
Register operand/memory operand. Number of times operation is repeated. Level of the stack frame. Conditional jump taken | Conditional jump not taken. (e.g. "4|1" = 4 clocks if jump taken, 1 clock if jump not taken) CPL IOPL \ CPL > IOPL (where CPL = Current Privilege Level, IOPL = I/O Privilege Level) Number of parameters passed on the stack.
6.4.3
CPU Instruction Set Summary Table Flags Table
The CPU Instruction Set Summary Table lists nine flags that are affected by the execution of instructions. The conventions shown in Table 6-18 are used to identify the different flags. Table 6-19 lists the conventions used to indicate what action the instruction has on the particular flag.
Table 6-18. Flag Abbreviations
ABBREVIATION NAME OF FLAG
OF DF IF TF SF ZF AF PF CF
Overflow Flag Direction Flag Interrupt Enable Flag Trap Flag Sign Flag Zero Flag Auxiliary Flag Parity Flag Carry Flag
Table 6-19. Action of Instruction on Flag
INSTRUCTION TABLE SYMBOL ACTION
x 0 1 u
Flag is modified by the instruction. Flag is not changed by the instruction. Flag is reset to "0". Flag is set to "1". Flag is undefined following execution of the instruction. PRELIMINARY 6-13
6-14
INSTRUCTION AAA ASCII Adjust AL after Add AAD ASCII Adjust AX before Divide AAS ASCII Adjust AL after Subtract ADC Add with Carry Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator ADD Integer Add Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator AND Boolean AND Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary
FLAGS OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
Advancing the Standards
37 D5 0A D4 0A 3F 1 [00dw] [11 reg r/m] 1 [000w] [mod reg r/m] 1 [001w] [mod reg r/m] 8 [00sw] [mod 010 r/m]### 1 [010w] ###
u u u u x
-
-
-
u x x u x
u x x u x u x x
u x x u x u x x x
7 7 13-21 7 1 1 1 1 1
7 7 13-21 7 b 1 1 1 1 1 b h 1 1 1 1 1 b h 1 1 1 1 1 9 a b, e h g,h,j,k,r h
®
AAM ASCII Adjust AX after Multiply
u x u
CPU Instruction Set Summary
x 0 [00dw] [11 reg r/m] 0 [000w] [mod reg r/m] 0 [001w] [mod reg r/m] 8 [00sw] [mod 000 r/m]### 0 [010w] ### 0 2 [00dw] [11 reg r/m] 2 [000w] [mod reg r/m] 2 [001w] [mod reg r/m] 8 [00sw] [mod 100 r/m]### 2 [010w] ### 63 [mod reg r/m] 62 [mod reg r/m] -
-
-
-
x
x x
x x 1 1 1 1 1
PRELIMINARY
-
-
-
x
x u
x 0 1 1 1 1 1
ARPL Adjust Requested Privilege Level From Register/Memory BOUND Check Array Boundaries If Out of Range (Int 5) If In Range BSF Scan Bit Forward Register, Register/Memory BSR Scan Bit Reverse Register, Register/Memory BSWAP Byte Swap BT Test Bit Register/Memory, Immediate Register/Memory, Register BTC Test Bit and Complement Register/Memory, Immediate Register/Memory, Register
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
-
-
-
-
x -
-
- - 20 11
20+INT 11 3 3 4 b h 2 5/6 b h 3 5/6 b b h h
0F BC [mod reg r/m] 0F BD [mod reg r/m] 0F C[1 reg] 0F BA [mod 100 r/m]# 0F A3 [mod reg r/m] 0F BA [mod 111 r/m]# 0F BB [mod reg r/m] -
-
-
-
-
x x - - -
- - - - x
3 3 4 2 5/6
-
-
-
-
- -
- x 3 5/6
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
- = unchanged
u = undefined
x = modified
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
BTR Test Bit and Reset Register/Memory, Immediate Register/Memory, Register BTS Test Bit and Set Register/Memory Register (short form) CALL Subroutine Call Direct Within Segment Register/Memory Indirect Within Segment Direct Intersegment Call Gate to Same Privilege Call Gate to Different Privilege No Parameters Call Gate to Different Privilege m Par's 16-bit Task to 16-bit TSS 16-bit Task to 32-bit TSS 16-bit Task to V86 Task 32-bit Task to 16-bit TSS 32-bit Task to 32-bit TSS 32-bit Task to V86 Task Indirect Intersegment Call Gate to Same Privilege Call Gate to Different Privilege No Parameters Call Gate to Different Privilege Level m Par's 16-bit Task to 16-bit TSS 16-bit Task to 32-bit TSS 16-bit Task to V86 Task 32-bit Task to 16-bit TSS 32-bit Task to 32-bit TSS 32-bit Task to V86 Task CBW Convert Byte to Word CDQ Convert Doubleword to Quadword CLC Clear Carry Flag CLD Clear Direction Flag CLI Clear Interrupt Flag CLTS Clear Task Switched Flag CMC Complement the Carry Flag
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
0F BA [mod 110 r/m]# 0F B3 [mod reg r/m] 0F BA [mod 101 r/m] 0F AB [mod reg r/m] E8 +++ FF [mod 010 r/m] 9A [unsigned full offset, selector]
-
-
-
-
- -
- x 3 5/6 3 5/6
b
h
-
-
-
-
- -
- x 3 5/6 3 5/6
b
h
-
-
-
-
- -
- 1 1/3 3 1 1/3 4 15 26 35+2m 110 118 96 112 120 98 8 20 31 40+2m 114 122 100 116 124 102 3 2 1 7 7 10 2
b
h,j,k,r
PRELIMINARY 6-15
FF [mod 011 r/m]
5
CPU Instruction Set Summary
98 99 F8 FC FA 0F 06 F5
-
0 -
0 -
-
-
- - - - - - - -
- - - 0 - - - - x
3 2 1 7 7 10 2
m c
x = modified
l
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
- = unchanged
u = undefined
6
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
6-16
CMPS Compare String
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Advancing the Standards
Real Protected Mode Mode
CMP Compare Integers Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator CMPXCHG Compare and Exchange Register1, Register2 Memory, Register CPUID CPU Identification CWD Convert Word to Doubleword CWDE Convert Word to Doubleword Extended DAA Decimal Adjust AL after Add
x 3 [10dw] [11 reg r/m] 3 [101w] [mod reg r/m] 3 [100w] [mod reg r/m] 8 [00sw] [mod 111 r/m] ### 3 [110w] ### A [011w] 0F B [000w] [11 reg2 reg1] 0F B [000w] [mod reg r/m] 0F A2 99 98 27 2F F [111w] [mod 001 r/m] 4 [1 reg] F [011w] [mod 110 r/m] x x x
-
-
-
x
x x
x x 1 1 1 1 1 1 1 1 1 1 5 11 11 12 2 2 9 9
b
h
®
CPU Instruction Set Summary
-
-
-
x x
x x x x
x x x x
5 11 11
b
h
-
-
-
x x x
- - - x x x x x x
- - - x x x x x -
12 2 2 9 9 1 1
PRELIMINARY
DAS Decimal Adjust AL after Subtract DEC Decrement by 1 Register/Memory Register (short form) DIV Unsigned Divide Accumulator by Register/Memory Divisor: Byte Word Doubleword ENTER Enter New Stack Frame Level = 0 Level = 1 Level (L) > 1 HLT Halt IDIV Integer (Signed) Divide Accumulator by Register/Memory Divisor: Byte Word Doubleword
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
-
-
b 1 1 b,e 13-17 13-25 13-41 13-17 13-25 13-41 b 10 13 10+L*3 10 13 10+L*3 5 b,e 16-20 16-28 17-45 16-20 16-28 17-45
x = modified - = unchanged u = undefined
h
-
-
-
x
x u
u -
e,h
C8 ##,#
-
-
-
-
-
- -
- -
h
F4 F [011w] [mod 111 r/m]
-
-
-
-
x
- -
-
-
5
l e,h
x u u -
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
IMUL Integer (Signed) Multiply Accumulator by Register/Memory Multiplier: Byte Word Doubleword Register with Register/Memory Multiplier: Word Doubleword Register/Memory with Immediate to Register2 Multiplier: Word Doubleword IN Input from I/O Port Fixed Port Variable Port INC Increment by 1 Register/Memory Register (short form) INS Input String from I/O Port INT Software Interrupt INT i Protected Mode: Interrupt or Trap to Same Privilege Interrupt or Trap to Different Privilege 16-bit Task to 16-bit TSS by Task Gate 16-bit Task to 32-bit TSS by Task Gate 16-bit Task to V86 by Task Gate 16-bit Task to 16-bit TSS by Task Gate 32-bit Task to 32-bit TSS by Task Gate 32-bit Task to V86 by Task Gate V86 to 16-bit TSS by Task Gate V86 to 32-bit TSS by Task Gate V86 to Privilege 0 by Trap Gate/Int Gate Continued on the next page...
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
x F [011w] [mod 101 r/m]
-
-
-
x
x u
u x 4 4 10 4 4 10 4 10 5 11
b
h
0F AF [mod reg r/m] 4 10 6 [10s1] [mod reg r/m] ### E [010w] [#] E [110w] x F [111w] [mod 000 r/m] 4 [0 reg] 6 [110w] CD # x 0 - - - - 9 21 32 114 122 100 116 124 102 124 102 46 x x x x 1 1 14 1 1 14/28 b b,e h,m g,j,k,r - - 14 14 14/28 14/28 b h 5 11
m
PRELIMINARY 6-17
CPU Instruction Set Summary
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
- = unchanged
u = undefined
x = modified
6
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
6-18
INVD Invalidate Cache
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Advancing the Standards
Real Protected Mode Mode
INT Software Interrupt (Continued) INT 3 INTO If OF==0 If OF==1 (INT 4) INVLPG Invalidate TLB Entry IRET Interrupt Return Real Mode Protected Mode: Within Task to Same Privilege Within Task to Different Privilege 16-bit Task to 16-bit Task 16-bit Task to 32-bit TSS 16-bit Task to V86 Task 32-bit Task to 16-bit TSS 32-bit Task to 32-bit TSS 32-bit Task to V86 Task JB/JNAE/JC Jump on Below/Not Above or Equal/ Carry 8-bit Displacement Full Displacement JBE/JNA Jump on Below or Equal/Not Above 8-bit Displacement Full Displacement JCXZ/JECXZ Jump on CX/ECX Zero JE/JZ Jump on Equal/Zero 8-bit Displacement Full Displacement JL/JNGE Jump on Less/Not Greater or Equal 8-bit Displacement Full Displacement JLE/JNG Jump on Less or Equal/Not Greater 8-bit Displacement Full Displacement
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
CC CE
-
x
0
-
- -
- INT 6 INT 6 15+INT 12 13
b,e
g,j,k,r
®
0F 08 0F 01 [mod 111 r/m] CF
x
x
x
x
x
x
x
- - x x
12 13 7
t
t g,h,j,k,r
CPU Instruction Set Summary
10 26 117 125 103 119 127 105 72 + 0F 82 +++ 76 + 0F 86 +++ E3 + 74 + 0F 84 +++ 7C + 0F 8C +++ 7E + 0F 8E +++
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
PRELIMINARY
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1 1 1 1
r
-
-
-
-
-
-
-
- - -
1 1 1
r r
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1
x = modified - = unchanged u = undefined
r
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
JMP Unconditional Jump 8-bit Displacement Full Displacement Register/Memory Indirect Within Segment Direct Intersegment Call Gate Same Privilege Level 16-bit Task to 16-bit TSS 16-bit Task to 32-bit TSS 16-bit Task to V86 Task 32-bit Task to 16-bit TSS 32-bit Task to 32-bit TSS 32-bit Task to V86 Task Indirect Intersegment Call Gate Same Privilege Level 16-bit Task to 16-bit TSS 16-bit Task to 32-bit TSS 16-bit Task to V86 Task 32-bit Task to 16-bit TSS 32-bit Task to 32-bit TSS 32-bit Task to V86 Task JNB/JAE/JNC Jump on Not Below/Above or Equal/ Not Carry 8-bit Displacement Full Displacement JNBE/JA Jump on Not Below or Equal/Above 8-bit Displacement Full Displacement JNE/JNZ Jump on Not Equal/Not Zero 8-bit Displacement Full Displacement JNL/JGE Jump on Not Less/Greater or Equal 8-bit Displacement Full Displacement JNLE/JG Jump on Not Less or Equal/Greater 8-bit Displacement Full Displacement
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
EB E9 FF EA + +++ [mod 100 r/m] [unsigned full offset, selector]
-
-
-
-
-
-
- 1 1 1/3 1 1 1 1/3 4 14 110 118 96 112 120 98 7 17 113 121 99 115 123 101
b
h,j,k,r
PRELIMINARY 6-19
FF [mod 101 r/m]
5
73 + 0F 83 +++ 77 + 0F 87 +++ 75 + 0F 85 +++ 7D + 0F 8D +++ 7F + 0F 8F +++
-
-
-
-
-
-
- 1 1 1 1
r
CPU Instruction Set Summary
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1
r
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
- = unchanged
u = undefined
x = modified
6
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
6-20
JNS Jump on Not Sign 8-bit Displacement Full Displacement JO Jump on Overflow 8-bit Displacement Full Displacement
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Advancing the Standards
Real Protected Mode Mode
JNO Jump on Not Overflow 8-bit Displacement Full Displacement JNP/JPO Jump on Not Parity/Parity Odd 8-bit Displacement Full Displacement
71 + 0F 81 +++ 7B + 0F 8B +++ 79 + 0F 89 +++ 70 + 0F 80 +++ 7A + 0F 8A +++ 78 + 0F 88 +++ 9F 0F 02 [mod reg r/m] C5 [mod reg r/m] 8D [mod reg r/m] -
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1
r
®
CPU Instruction Set Summary
-
-
-
-
-
-
- 1 1 1 1
r
-
-
-
-
-
-
- 1 1 1 1
r
JP/JPE Jump on Parity/Parity Even 8-bit Displacement Full Displacement JS Jump on Sign 8-bit Displacement Full Displacement LAHF Load AH with Flags LAR Load Access Rights From Register/Memory LDS Load Pointer to DS LEA Load Effective Address No Index Register With Index Register LEAVE Leave Current Stack Frame LES Load Pointer to ES LFS Load Pointer to FS LGDT Load GDT Register LGS Load Pointer to GS LIDT Load IDT Register LLDT Load LDT Register From Register/Memory LMSW Load Machine Status Word From Register/Memory LODS Load String LOOP Offset Loop/No Loop
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
-
-
-
-
-
-
- 1 1 1 1
r
PRELIMINARY
-
-
-
-
-
-
- 1 1 1 1 2 a 8 2 1 1 4 1 1 4 4 4 8 4 8 5 b,c 13 13 3 1
x = modified - = unchanged u = undefined
r
-
-
-
-
x -
-
- - - - -
2
g,h,j,p h,i,j
b
C9 C4 [mod reg r/m] 0F B4 [mod reg r/m] 0F 01 [mod 010 r/m] 0F B5 [mod reg r/m] 0F 01 [mod 011 r/m] 0F 00 [mod 010 r/m]
-
-
-
-
-
-
-
- - - - - - - -
4 2 2 8 2 8 5
b b b b,c b b,c a
h h,i,j h,i,j h,l h,i,j h,l g,h,j,l h,l h r
- - - 3 1
0F 01 [mod 110 r/m] A [110 w] E2 + -
b
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
LOOPNZ/LOOPNE Offset LOOPZ/LOOPE Offset LSL Load Segment Limit From Register/Memory LSS Load Pointer to SS LTR Load Task Register From Register/Memory MOV Move Data Register to Register Register to Memory Register/Memory to Register Immediate to Register/Memory Immediate to Register (short form) Memory to Accumulator (short form) Accumulator to Memory (short form) Register/Memory to Segment Register Segment Register to Register/Memory MOV Move to/from Control/Debug/Test Regs Register to CR0/CR2/CR3 CR0/CR2/CR3 to Register Register to DR0-DR3 DR0-DR3 to Register Register to DR6-DR7 DR6-DR7 to Register Register to TR3-5 TR3-5 to Register Register to TR6-TR7 TR6-TR7 to Register MOVS Move String MOVSX Move with Sign Extension Register from Register/Memory MOVZX Move with Zero Extension Register from Register/Memory
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
E0 + E1 + 0F 03 [mod reg r/m] 0F B2 [mod reg r/m] 0F 00 [mod 011 r/m]
-
-
-
-
-
x -
-
- - - -
1 1
1 1 a 8
r r g,h,j,p h,i,j g,h,j,l h,i,j
- - -
2
4 7
a a b
- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1/3 1
8 [10dw] [11 reg r/m] 8 [100w] [mod reg r/m] 8 [101w] [mod reg r/m] C [011w] [mod 000 r/m] ### B [w reg] ### A [000w] +++ A [001w] +++ 8E [mod sreg3 r/m] 8C [mod sreg3 r/m] 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 22 [11 eee reg] 20 [11 eee reg] 23 [11 eee reg] 21 [11 eee reg] 23 [11 eee reg] 21 [11 eee reg] 26 [11 eee reg] 24 [11 eee reg] 26 [11 eee reg] 24 [11 eee reg] 0F B[111w] [mod reg r/m] 0F B[011w] [mod reg r/m]
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
PRELIMINARY 6-21
-
-
-
-
-
-
- 20/5/5 6 16 14 16 14 10 5 10 6 20/5/5 6 16 14 16 14 10 5 10 6 4 1 b 1 1 b b 1
l
CPU Instruction Set Summary
A [010w]
-
-
-
-
-
-
- - - -
4
h h h
- = unchanged
u = undefined
x = modified
6
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
6-22
NEG Negate Integer NOP No Operation
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Advancing the Standards
Real Protected Mode Mode
MUL Unsigned Multiply Accumulator with Register/Memory Multiplier: Byte Word Doubleword
F [011w] [mod 100 r/m]
x
-
-
-
x
x u
u x 4 4 10 4 4 10 1 1 1 8 - 125
b
h
®
F [011w] [mod 011 r/m] 90 F [011w] [mod 010 r/m] 0F FF 0 0 0 8 0 [10dw] [11 reg r/m] [100w] [mod reg r/m] [101w] [mod reg r/m] [00sw] [mod 001 r/m] ### [110w] ###
x 0
-
x -
0 -
x x
x x
x u
x x - - - x 0
1 1 1 1 1 1 1 1 1
b b b
h h h
CPU Instruction Set Summary
NOT Boolean Complement OIO Official Invalid OpCode OR Boolean OR Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator OUT Output to Port Fixed Port Variable Port OUTS Output String POP Pop Value off Stack Register/Memory Register (short form) Segment Register (ES, SS, DS) Segment Register (FS, GS) POPA Pop All General Registers POPF Pop Stack into FLAGS PREFIX BYTES Assert Hardware LOCK Prefix Address Size Prefix Operand Size Prefix Segment Override Prefix CS DS ES FS GS SS
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
1 1 1 1 1 m 14/28 14/28 14/28 1 1 3 3 6 9 b b h h,n m b b h,m h,i,j
PRELIMINARY
E [011w] # E [111w] 6 [111w] 8F [mod 000 r/m] 5 [1 reg] [000 sreg2 111] 0F [10 sreg3 001] 61 9D F0 67 66 2E 3E 26 64 65 36 x -
-
-
-
-
-
-
- 14 14
-
-
-
-
-
-
- - -
14 1 1 1 1
x -
x -
x -
x -
x -
x -
- x x - -
6 9
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
x = modified - = unchanged u = undefined
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
PUSH Push Value onto Stack Register/Memory Register (short form) Segment Register (ES, CS, SS, DS) Segment Register (FS, GS) Immediate PUSHA Push All General Registers PUSHF Push FLAGS Register RCL Rotate Through Carry Left Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate RCR Rotate Through Carry Right Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate REP INS Input String REP LODS Load String REP MOVS Move String REP OUTS Output String REP STOS Store String REPE CMPS Compare String (Find non-match) REPE SCAS Scan String (Find non-AL/AX/EAX) REPNE CMPS Compare String (Find match) REPNE SCAS Scan String (Find AL/AX/EAX) RET Return from Subroutine Within Segment Within Segment Adding Immediate to SP Intersegment Intersegment Adding Immediate to SP Protected Mode: Different Privilege Level Intersegment Intersegment Adding Immediate to SP
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
FF [mod 110 r/m] 5 [0 reg] [000 sreg2 110] 0F [10 sreg3 000] 6 [10s0] ### 60 9C D [000w] [mod 010 r/m] D [001w] [mod 010 r/m] C [000w] [mod 010 r/m] # D [000w] [mod 011 r/m] D [001w] [mod 011 r/m] C [000w] [mod 011 r/m] # F3 6[110w] F3 A[110w] F3 A[010w] F3 6[111w] F3 A[101w] F3 A[011w] F3 A[111w] F2 A[011w] F2 A[111w] x u u x u u x x x x C3 C2 ## CB CA ##
-
-
-
-
-
-
- 1 1 1 1 1 1 1 1 1 1 6 2 3 8 8
b
h
-
-
-
x x x x -
x x x x -
x x x x -
- - - x - x - x - x - x - x - - - - - x x
6 2 3 8 8 4 9 9 12+5n 10+n 9+n 12+5n 10+n 10+2n
b b b
h h h
PRELIMINARY 6-23
b 4 9 9 12+5n\ 28+5n 10+n 9+n 12+5n\ 28+5n 10+n 10+2n 10+2n 10+2n 10+2n b b b b 3 4 4 4 3 4 7 7 23 23
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
h
b b b b b b
h,m h h h,m h h h h h g,h,j,k,r
CPU Instruction Set Summary
x x x x x x - -
10+2n 10+2n 10+2n
6
- = unchanged
u = undefined
x = modified
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
6-24 PRELIMINARY
SCAS Scan String
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Advancing the Standards
Real Protected Mode Mode
ROL Rotate Left Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate ROR Rotate Right Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate RSDC Restore Segment Register and Descriptor RSLDT Restore LDTR and Descriptor RSM Resume from SMM Mode RSTS Restore TSR and Descriptor SAHF Store AH in FLAGS SAL Shift Left Arithmetic Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate SAR Shift Right Arithmetic Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate SBB Integer Subtract with Borrow Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator (short form) SETB/SETNAE/SETC Set Byte on Below/Not Above or Equal/Carry To Register/Memory SETBE/SETNA Set Byte on Below or Equal/Not Above To Register/Memory SETE/SETZ Set Byte on Equal/Zero To Register/Memory SETL/SETNGE Set Byte on Less/Not Greater or Equal To Register/Memory
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
b D[000w] [mod 000 r/m] D[001w] [mod 000 r/m] C[000w] [mod 000 r/m] # D[000w] [mod 001 r/m] D[001w] [mod 001 r/m] C[000w] [mod 001 r/m] # 0F 79 [mod sreg3 r/m] 0F 7B [mod 000 r/m] 0F AA 0F 7D [mod 000 r/m] 9E D[000w] [mod 100 r/m] D[001w] [mod 100 r/m] C[000w] [mod 100 r/m] # D[000w] [mod 111 r/m] D[001w] [mod 111 r/m] C[000w] [mod 111 r/m] # 1[10dw] [11 reg r/m] 1[100w] [mod reg r/m] 1[101w] [mod reg r/m] 8[00sw] [mod 011 r/m] ### 1[110w] ### A [111w] x 0F 92 [mod 000 r/m] 0F 96 [mod 000 r/m] 0F 94 [mod 000 r/m] 0F 9C [mod 000 r/m]
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
h
x u u x u u x x u u x u u x -
x -
-
-
x x
x x
x x u u u u u u x
- x - x - x - x - x - x - - x x - x x x x x x x x x x x x x x x x
1 2 1 1 2 1 6 6 40 6 1 1 2 1 1 2 1 1 1 1 1 1
1 2 1 b 1 2 1 6 6 40 6 1 b h 1 2 1 b h 1 2 1 b 1 1 1 1 1 2 b h h h s s s s s s s s h
®
CPU Instruction Set Summary
x x
-
-
-
x x x x x x
- x x - x x - x x x x
-
-
-
x -
x -
x -
x x - -
2
1 - 1 - 1 - 1
1 h 1 h 1 h 1
- = unchanged
u = undefined
x = modified
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
SETLE/SETNG Set Byte on Less or Equal/Not Greater To Register/Memory SETNB/SETAE/SETNC Set Byte on Not Below/ Above or Equal/Not Carry To Register/Memory SETNBE/SETA Set Byte on Not Below or Equal/Above To Register/Memory SETNE/SETNZ Set Byte on Not Equal/Not Zero To Register/Memory SETNL/SETGE Set Byte on Not Less/Greater or Equal To Register/Memory SETNLE/SETG Set Byte on Not Less or Equal/Greater To Register/Memory SETNO Set Byte on Not Overflow To Register/Memory SETNP/SETPO Set Byte on Not Parity/Parity Odd To Register/Memory SETNS Set Byte on Not Sign To Register/Memory SETO Set Byte on Overflow To Register/Memory SETP/SETPE Set Byte on Parity/Parity Even To Register/Memory SETS Set Byte on Sign To Register/Memory SGDT Store GDT Register To Register/Memory SHL Shift Left Logical Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate SHLD Shift Left Double Register/Memory by Immediate Register/Memory by CL
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
0F 9E [mod 000 r/m] 0F 93 [mod 000 r/m] 0F 97 [mod 000 r/m] 0F 95 [mod 000 r/m] 0F 9D [mod 000 r/m] 0F 9F [mod 000 r/m] 0F 91 [mod 000 r/m] 0F 9B [mod 000 r/m] 0F 99 [mod 000 r/m] 0F 90 [mod 000 r/m] 0F 9A [mod 000 r/m] 0F 98 [mod 000 r/m] 0F 01 [mod 000 r/m]
-
-
-
-
-
-
- 1 1
h
-
-
-
-
-
-
- 1 1
h
-
-
-
-
-
-
- 1 1
h
-
-
-
-
-
-
- 1 - 1 1 1
h h
PRELIMINARY 6-25
-
-
-
-
-
-
- 1 1
h
-
-
-
-
-
-
- 1 - 1 1 1
h h
CPU Instruction Set Summary
-
-
-
-
-
-
- 1 - 1 - 1 - 1 - 4 1 4 b,c b 1 1 1
h h h h h h
D [000w] [mod 100 r/m] D [001w] [mod 100 r/m] C [000w] [mod 100 r/m] # 0F A4 [mod reg r/m] # 0F A5 [mod reg r/m]
x u u u
-
-
-
x x x x x x x x
u u u u
x x x x x x x x
1 2 1 4 5
1 2 1 b 4 5 h
6
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
- = unchanged
u = undefined
x = modified
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
6-26
SIDT Store IDT Register To Register/Memory SLDT Store LDT Register To Register/Memory STC Set Carry Flag
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Advancing the Standards
Real Protected Mode Mode
SHR Shift Right Logical Register/Memory by 1 Register/Memory by CL Register/Memory by Immediate SHRD Shift Right Double Register/Memory by Immediate Register/Memory by CL
b D [000w] [mod 101 r/m] D [001w] [mod 101 r/m] C [000w] [mod 101 r/m] # 0F AC [mod reg r/m] # 0F AD [mod reg r/m] 0F 01 [mod 001 r/m] 0F 00 [mod 000 r/m] 0F 7E 0F 01 [mod 100 r/m] F9 FD FB A [101w] 0F 00 [mod 001 r/m] x 2 2 2 8 2 [10dw] [11 reg r/m] [100w] [mod reg r/m] [101w] [mod reg r/m] [00sw] [mod 101 r/m] ### [110w] ### 0 8 [010w] [mod reg r/m] F [011w] [mod 000 r/m] ### A [100w] ### 0F 00 [mod 100 r/m] 0F 00 [mod 101 r/m] 9B - 5
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
h
x u u u
-
-
-
x x x x x x x x
u u u u
x x x x x x x x
1 2 1 4 5
1 2 1 b 4 5 b,c h h s h 4 a 1 h
®
CPU Instruction Set Summary
1 -
1 -
-
x
x
x
- 4 - - - - 1 - - - - 4 x x 1 1 1 1 1 1 1 1 1 1 12 12 14 1 1 1 55 6 1 7 7 2 55 6 1 7 7 2
SMINT Software SMM Entry SMSW Store Machine Status Word
-
s b,c
PRELIMINARY
STD Set Direction Flag STI Set Interrupt Flag STOS Store String STR Store Task Register To Register/Memory SUB Integer Subtract Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator (short form) SVDC Save Segment Register and Descriptor SVLDT Save LDTR and Descriptor SVTS Save TSR and Descriptor TEST Test Bits Register/Memory and Register Immediate Data and Register/Memory Immediate Data and Accumulator VERR Verify Read Access To Register/Memory VERW Verify Write Access To Register/Memory WAIT Wait Until FPU Not Busy
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
m b a b h h h
0F 78 [mod sreg3 r/m] 0F 7A [mod 000 r/m] 0F 7C [mod 000 r/m]
-
-
-
x
x
u
- - - x 0
12 12 14 1 1 1
s s s b
s s s h
-
-
-
-
x x
-
- 7 - 7 5
a a
g,h,j,p g,h,j,p
- = unchanged
u = undefined
x = modified
Table 6-20. 6x86 CPU Instruction Set Clock Count Summary (Continued)
FLAGS INSTRUCTION OPCODE
OF DF IF TF SF ZF AF PF CF
REAL MODE CLOCK COUNT
Reg/ Cache Hit
PROTECTED MODE CLOCK COUNT
Reg/ Cache Hit
NOTES
Real Protected Mode Mode
WBINVD Write-Back and Invalidate Cache XADD Exchange and Add Register1, Register2 Memory, Register XCHG Exchange Register/Memory with Register Register with Accumulator XLAT Translate Byte XOR Boolean Exclusive OR Register to Register Register to Memory Memory to Register Immediate to Register/Memory Immediate to Accumulator (short form)
# = immediate 8-bit data ## = immediate 16-bit data ### = full immediate 32-bit data (8, 16, 32 bits)
0F 09
x
-
-
-
x
x
x
- x x
15
15
t
t
0F C[000w] [11 reg2 reg1] 0F C[000w] [mod reg r/m] 8[011w] [mod reg r/m] 9[0 reg] D7 3 [00dw] [11 reg r/m] 3 [000w] [mod reg r/m] 3 [001w] [mod reg r/m] 8 [00sw] [mod 110 r/m] ### 3 [010w] ###
+ = 8-bit signed displacement +++ = full signed displacement (16, 32 bits)
2 2 - 2 2 0 x x u - x 0 1 1 1 1 1 4
2 2 b,f 2 2 4 b 1 1 1 1 1 h h f,h
PRELIMINARY 6-27
- = unchanged
u = undefined
x = modified
Instruction Notes for Instruction Set Summary
CPU Instruction Set Summary
Notes a through c apply to Real Address Mode only: a. This is a Protected Mode instruction. Attempted execution in Real Mode will result in exception 6 (invalid op-code). b. Exception 13 fault (general protection) will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum CS, DS, ES, FS, or GS segment limit (FFFFH). Exception 12 fault (stack segment limit violation or not present) will occur in Real Mode if an operand reference is made that partially or fully extends beyond the maximum SS limit. c. This instruction may be executed in Real Mode. In Real Mode, its purpose is primarily to initialize the CPU for Protected Mode. d. Notes e through g apply to Real Address Mode and Protected Virtual Address Mode: e. An exception may occur, depending on the value of the operand. f. LOCK# is automatically asserted, regardless of the presence or absence of the LOCK prefix. g. LOCK# is asserted during descriptor table accesses. Notes h through r apply to Protected Virtual Address Mode only: h. Exception 13 fault will occur if the memory operand in CS, DS, ES, FS, or GS cannot be used due to either a segment limit violation or an access rights violation. If a stack limit is violated, an exception 12 occurs. i. For segment load operations, the CPL, RPL, and DPL must agree with the privilege rules to avoid an exception 13 fault. The segment's descriptor must indicate "present" or exception 11 (CS, DS, ES, FS, GS not present). If the SS register is loaded and a stack segment not present is detected, an exception 12 occurs. Continued on next page...
6
j. k. l. m. n. o. p. q.
All segment descriptor accesses in the GDT or LDT made by this instruction will automatically assert LOCK# to maintain descriptor integrity in multiprocessor systems. JMP, CALL, INT, RET, and IRET instructions referring to another code segment will cause an exception 13, if an applicable privilege rule is violated. An exception 13 fault occurs if CPL is greater than 0 (0 is the most privileged level). An exception 13 fault occurs if CPL is greater than IOPL. The IF bit of the flag register is not updated if CPL is greater than IOPL. The IOPL and VM fields of the flag register are updated only if CPL = 0. The PE bit of the MSW (CR0) cannot be reset by this instruction. Use MOV into CRO if desiring to reset the PE bit. Any violation of privilege rules as apply to the selector operand does not cause a Protection exception, rather, the zero flag is cleared. If the coprocessor's memory operand violates a segment limit or segment access rights, an exception 13 fault will occur before the ESC instruction is executed. An exception 12 fault will occur if the stack limit is violated by the operand's starting address. r. The destination of a JMP, CALL, INT, RET, or IRET must be in the defined limit of a code segment or an exception 13 fault will occur. Note s applies to Cyrix specific SMM instructions: s. All memory accesses to SMM space are non-cacheable. An invalid opcode exception 6 occurs unless SMI is enabled and ARR3 size > 0, and CPL = 0 and [SMAC is set or if in an SMI handler]. Note t applies to cache invalidation instructions with the cache operating in write-back mode: t. The total clock count is the clock count shown plus the number of clocks required to write all "modified" cache lines to external memory.
6-28 PRELIMINARY
Advancing the Standards
®
CPU Instruction Set Summary
FPU Clock Counts
6
6.5
FPU Clock Counts
The CPU is functionally divided into the FPU, and the integer unit. The FPU processes floating point instructions only and does so in parallel with the integer unit. For example, when the integer unit detects a floating point instruction without memory operands, after two clock cycles the instruction passes to the FPU for execution. The integer unit continues to execute instructions while the FPU executes the floating point instruction. If
another FPU instruction is encountered, the second FPU instruction is placed in the FPU queue. Up to four FPU instructions can be queued. In the event of an FPU exception, while other FPU instructions are queued, the state of the CPU is saved to ensure recovery. 6.5.1 FPU Clock Count Table
The clock counts for the FPU instructions are listed in Table 6-19 (Page 13). The abbreviations used in this table are listed in Table 6-21.
Table 6-21. FPU Clock Count Table Abbreviations
ABBREVIATION MEANING
n TOS ST(1) ST(n) M.WI M.SI M.LI M.SR M.DR M.XR M.BCD CC Env Regs
Stack register number Top of stack register pointed to by SSS in the status register. FPU register next to TOS A specific FPU register, relative to TOS 16-bit integer operand from memory 32-bit integer operand from memory 64-bit integer operand from memory 32-bit real operand from memory 64-bit real operand from memory 80-bit real operand from memory 18-digit BCD integer operand from memory FPU condition code Status, Mode Control and Tag Registers, Instruction Pointer and Operand Pointer
PRELIMINARY
6-29
6-30
FPU INSTRUCTION F2XM1 Function Evaluation 2x-1 FABS Floating Absolute Value FADD Floating Point Add Top of Stack 80-bit Register 64-bit Real 32-bit Real FADDP Floating Point Add, Pop FIADD Floating Point Integer Add 32-bit integer 16-bit integer FCHS Floating Change Sign FCLEX Clear Exceptions FNCLEX Clear Exceptions FCOM Floating Point Compare 80-bit Register 64-bit Real 32-bit Real FCOMP Floating Point Compare, Pop 80-bit Register 64-bit Real 32-bit Real FCOMPP Floating Point Compare, Pop Two Stack Elements FICOM Floating Point Compare 32-bit integer 16-bit integer FICOMP Floating Point Compare 32-bit integer 16-bit integer FCOS Function Evaluation: Cos(x) FDECSTP Decrement Stack Pointer FDIV Floating Point Divide Top of Stack 80-bit Register 64-bit Real 32-bit Real FDIVP Floating Point Divide, Pop FDIVR Floating Point Divide Reversed Top of Stack 80-bit Register 64-bit Real 32-bit Real
Table 6-22. 6x86 FPU Instruction Set Summary
OP CODE D9 F0 D9 E1 DC D8 DC D8 DE [1100 0 n] [1100 0 n] [mod 000 r/m] [mod 000 r/m] [1100 0 n] OPERATION TOS <----- 2TOS-1 TOS <----- | TOS | ST(n) TOS TOS TOS ST(n) <----<----<----<----<----ST(n) + TOS TOS + ST(n) TOS + M.DR TOS + M.SR ST(n) + TOS; then pop TOS CLOCK COUNT 92 - 108 2 4-9 4-9 4-9 4-9 4-9 8 - 14 8 - 14 2 5 3 4 4 4 4 4 4 4 9 - 10 9 - 10 9 - 10 9 - 10 92 - 141 4 24 - 34 24 - 34 24 - 34 24 - 34 24 - 34 24 - 34 24 - 34 24 - 34 24 - 34 See Note 1 NOTES See Note 2
Advancing the Standards
®
FPU Clock Counts
DA [mod 000 r/m] DE [mod 000 r/m] D9 E0 (9B)DB E2 DB E2 D8 [1101 0 n] DC [mod 010 r/m] D8 [mod 010 r/m] D8 [1101 1 n] DC [mod 011 r/m] D8 [mod 011 r/m] DE D9 DA [mod 010 r/m] DE [mod 010 r/m] DA [mod 011 r/m] DE [mod 011 r/m] D9 FF D9 F6 DC D8 DC D8 DE DC D8 DC D8 [1111 1 n] [1111 0 n] [mod 110 r/m] [mod 110 r/m] [1111 1 n] [1111 0 n] [1111 1 n] [mod 111 r/m] [mod 111 r/m]
TOS <----- TOS + M.SI TOS <----- TOS + M.WI TOS <----- - TOS Wait then Clear Exceptions Clear Exceptions CC set by TOS - ST(n) CC set by TOS - M.DR CC set by TOS - M.SR CC set by TOS - ST(n); then pop TOS CC set by TOS - M.DR; then pop TOS CC set by TOS - M.SR; then pop TOS CC set by TOS - ST(1); then pop TOS and ST(1) CC set by TOS - M.WI CC set by TOS - M.SI CC set by TOS - M.WI; then pop TOS CC set by TOS - M.SI; then pop TOS TOS <------ COS(TOS) Decrement top of stack pointer ST(n) TOS TOS TOS ST(n) TOS ST(n) TOS TOS <----<----<----<----<----<----<----<----<----ST(n) / TOS TOS / ST(n) TOS / M.DR TOS / M.SR ST(n) / TOS; then pop TOS ST(n) / TOS TOS / ST(n) M.DR / TOS M.SR / TOS
PRELIMINARY
Table 6-22. 6x86 FPU Instruction Set Summary
FPU INSTRUCTION FDIVRP Floating Point Divide Reversed, Pop FIDIV Floating Point Integer Divide 32-bit Integer 16-bit Integer FIDIVR Floating Point Integer Divide Reversed 32-bit Integer 16-bit Integer FFREE Free Floating Point Register FINCSTP Increment Stack Pointer FINIT Initialize FPU FNINIT Initialize FPU FLD Load Data to FPU Reg. Top of Stack 64-bit Real 32-bit Real FBLD Load Packed BCD Data to FPU Reg. FILD Load Integer Data to FPU Reg. 64-bit Integer 32-bit Integer 16-bit Integer FLD1 Load Floating Const.= 1.0 FLDCW Load FPU Mode Control Register FLDENV Load FPU Environment FLDL2E Load Floating Const.= Log2(e) FLDL2T Load Floating Const.= Log2(10) FLDLG2 Load Floating Const.= Log10(2) FLDLN2 Load Floating Const.= Ln(2) FLDPI Load Floating Const.= FLDZ Load Floating Const.= 0.0 FMUL Floating Point Multiply Top of Stack 80-bit Register 64-bit Real 32-bit Real FMULP Floating Point Multiply & Pop FIMUL Floating Point Integer Multiply 32-bit Integer 16-bit Integer FNOP No Operation OP CODE DE [1111 0 n] DA [mod 110 r/m] DE [mod 110 r/m] OPERATION ST(n) <----- TOS / ST(n); then pop TOS TOS <----- TOS / M.SI TOS <----- TOS / M.WI -
(Continued)
CLOCK COUNT 24 - 34 34 - 38 33 - 38 NOTES
DA [mod 111 r/m] DE [mod 111 r/m] DD [1100 0 n] D9 F7 (9B)DB E3 DB E3 D9 [1100 0 n] DD [mod 000 r/m] D9 [mod 000 r/m] DF [mod 100 r/m] DF [mod 101 r/m] DB [mod 000 r/m] DF [mod 000 r/m] D9 E8 D9 [mod 101 r/m] D9 [mod 100 r/m] D9 D9 D9 D9 D9 D9 EA E9 EC ED EB EE
TOS <----- M.SI / TOS TOS <----- M.WI / TOS TAG(n) <----- Empty Increment top of stack pointer Wait then initialize Initialize Push ST(n) onto stack Push M.DR onto stack Push M.SR onto stack Push M.BCD onto stack Push M.LI onto stack Push M.SI onto stack Push M.WI onto stack Push 1.0 onto stack Ctl Word <----- Memory Env Regs <----- Memory Push Log2(e) onto stack Push Log2(10) onto stack Push Log10(2) onto stack Push Loge(2) onto stack Push onto stack Push 0.0 onto stack ST(n) TOS TOS TOS ST(n) <----<----<----<----<----ST(n) × TOS TOS × ST(n) TOS × M.DR TOS × M.SR ST(n) × TOS; then pop TOS
34 - 38 33 - 38 3 2 8 6 2 2 2 41 - 45 4-8 4-6 3-6 4 4 30 4 4 4 4 4 4 4-9 4-9 4-8 4-6 4-9 9 - 11 8 - 10 2
PRELIMINARY 6-31
FPU Clock Counts
DC [1100 1 n] D8 [1100 1 n] DC [mod 001 r/m] D8 [mod 001 r/m] DE [1100 1 n] DA [mod 001 r/m] DE [mod 001 r/m] D9 D0
TOS <----- TOS × M.SI TOS <----- TOS × M.WI No Operation
6
Table 6-22. 6x86 FPU Instruction Set Summary
FPU INSTRUCTION FPATAN Function Eval: Tan (y/x) FPREM Floating Point Remainder FPREM1 Floating Point Remainder IEEE FPTAN Function Eval: Tan(x) FRNDINT Round to Integer FRSTOR Load FPU Environment and Reg. FSAVE Save FPU Environment and Reg FNSAVE Save FPU Environment and Reg FSCALE Floating Multiply by 2n FSIN Function Evaluation: Sin(x) FSINCOS Function Eval.: Sin(x)& Cos(x)
-1
(Continued)
CLOCK COUNT 97 - 161 82 - 91 82 - 91 117 - 129 10 - 20 56 - 72 57 - 67 55 - 65 7 - 14 76 - 140 145 - 161 See Note 1 See Note 1 NOTES See Note 3
Advancing the Standards
6-32 PRELIMINARY
OP CODE D9 D9 D9 D9 D9 F3 F8 F5 F2 FC ST(1) TOS TOS TOS TOS <----<----<----<----<-----
OPERATION ATAN[ST(1) / TOS]; then pop TOS Rem[TOS / ST(1)] Rem[TOS / ST(1)] TAN(TOS); then push 1.0 onto stack Round(TOS)
See Note 1
DD [mod 100 r/m] (9B)DD[mod 110 r/m] DD [mod 110 r/m] D9 FD D9 FE D9 FB
Restore state. Wait then save state. Save state. TOS <----- TOS × 2(ST(1)) TOS <----- SIN(TOS) temp <----- TOS; TOS <----- SIN(temp); then push COS(temp) onto stack TOS <----- Square Root of TOS ST(n) M.XR M.DR M.SR ST(n) M.XR M.DR M.SR M.BCD <----<----<----<----<----<----<----<----<----TOS TOS TOS TOS TOS; TOS; TOS; TOS; TOS; then pop TOS then pop TOS then pop TOS then pop TOS then pop TOS
®
FPU Clock Counts
FSQRT Floating Point Square Root FST Store FPU Register Top of Stack 80-bit Real 64-bit Real 32-bit Real FSTP Store FPU Register, Pop Top of Stack 80-bit Real 64-bit Real 32-bit Real FBSTP Store BCD Data, Pop FIST Store Integer FPU Register 32-bit Integer 16-bit Integer FISTP Store Integer FPU Register, Pop 64-bit Integer 32-bit Integer 16-bit Integer FSTCW Store FPU Mode Control Register FNSTCW Store FPU Mode Control Register FSTENV Store FPU Environment FNSTENV Store FPU Environment FSTSW Store FPU Status Register FNSTSW Store FPU Status Register FSTSW AX Store FPU Status Register to AX FNSTSW AX Store FPU Status Register to AX
D9 FA DD [1101 0 n] DB [mod 111 r/m] DD [mod 010 r/m] D9 [mod 010 r/m] DB [1101 1 n] DB [mod 111 r/m] DD [mod 011 r/m] D9 [mod 011 r/m] DF [mod 110 r/m] DB [mod 010 r/m] DF [mod 010 r/m] DF [mod 111 r/m] DB [mod 011 r/m] DF [mod 011 r/m] (9B)D9[mod 111 r/m] D9 [mod 111 r/m] (9B)D9[mod 110 r/m] D9 [mod 110 r/m] (9B)DD[mod 111 r/m] DD [mod 111 r/m] (9B)DF E0 DF E0
59 - 60 2 2 2 2 2 2 2 2 57 - 63 8 - 13 7 - 10 10 - 13 8 - 13 7 - 10 5 3 14 - 24 12 - 22 6 4 4 2
M.SI <----- TOS M.WI <----- TOS M.LI <----- TOS; then pop TOS M.SI <----- TOS; then pop TOS M.WI <----- TOS; then pop TOS Wait Memory Memory Wait Memory Memory Wait Memory Memory Wait AX AX <----<----<----<----<----<----<----<----Control Mode Register Control Mode Register Env. Registers Env. Registers Status Register Status Register Status Register Status Register
Table 6-22. 6x86 FPU Instruction Set Summary
FPU INSTRUCTION FSUB Floating Point Subtract Top of Stack 80-bit Register 64-bit Real 32-bit Real FSUBP Floating Point Subtract, Pop FSUBR Floating Point Subtract Reverse Top of Stack 80-bit Register 64-bit Real 32-bit Real FSUBRP Floating Point Subtract Reverse, Pop FISUB Floating Point Integer Subtract 32-bit Integer 16-bit Integer FISUBR Floating Point Integer Subtract Reverse 32-bit Integer Reversed 16-bit Integer Reversed FTST Test Top of Stack FUCOM Unordered Compare FUCOMP Unordered Compare, Pop FUCOMPP Unordered Compare, Pop two elements FWAIT Wait FXAM Report Class of Operand FXCH Exchange Register with TOS FXTRACT Extract Exponent OP CODE DC [1110 1 n] D8 [1110 0 n] DC [mod 100 r/m] D8 [mod 100 r/m] DE [1110 1 n] DC [1110 0 n] D8 [1110 1 n] DC [mod 101 r/m] D8 [mod 101 r/m] DE [1110 0 n] ST(n) TOS TOS TOS ST(n) TOS ST(n) TOS TOS ST(n) <----<----<----<----<----<----<----<----<----<----OPERATION ST(n) - TOS TOS - ST(n) TOS - M.DR TOS - M.SR ST(n) - TOS; then pop TOS ST(n) - TOS TOS - ST(n) M.DR - TOS M.SR - TOS TOS - ST(n); then pop TOS
(Continued)
CLOCK COUNT 4-9 4-9 4-9 4-9 4-9 4-9 4-9 4-9 4-9 4-9 NOTES
PRELIMINARY 6-33
DA [mod 100 r/m] DE [mod 100 r/m]
TOS <----- TOS - M.SI TOS <----- TOS - M.WI -
14 - 29 14 - 27
DA [mod 101 r/m] DE [mod 101 r/m] D9 E4 DD [1110 0 n] DD [1110 1 n] DA E9 9B D9 E5 D9 [1100 1 n] D9 F4
TOS <----- M.SI - TOS TOS <----- M.WI - TOS CC set by TOS - 0.0 CC set by TOS - ST(n) CC set by TOS - ST(n); then pop TOS CC set by TOS - ST(I); then pop TOS and ST(1) Wait for FPU not busy CC <----- Class of TOS TOS - ----- ST(n) Exchange < > temp <----- TOS; TOS <----- exponent (temp); then push significant (temp) onto stack ST(1) <----- ST(1) × Log2(TOS); then pop TOS ST(1) <----- ST(1) × Log2(1+TOS); then pop TOS -
14 - 29 14 - 27 4 4 4 4 2 4 3 11 - 16
FPU Clock Counts
FLY2X Function Eval. y × Log2(x) FLY2XP1 Function Eval. y × Log2(x+1)
D9 F1 D9 F9
145 - 154 131 - 133
See Note 4
6
6-34 PRELIMINARY
FPU Instruction Summary Notes All references to TOS and ST(n) refer to stack layout prior to execution. Values popped off the stack are discarded. A pop from the stack increments the top of stack pointer. A push to the stack decrements the top of stack pointer. Note 1: For FCOS, FSIN, FSINCOS and FPTAN, time shown is for absolute value of TOS < 3/4. Add 90 clock counts for argument reduction if outside this range. For FCOS, clock count is 141 if TOS < /4 and clock count is 92 if /4 < TOS > /2. For FSIN, clock count is 81 to 82 if absolute value of TOS < /4. Note 2: For F2XM1, clock count is 92 if absolute value of TOS < 0.5. Note 3: For FPATAN, clock count is 97 if ST(1)/TOS < /32. Note 4: For FYL2XP1, clock count is 170 if TOS is out of range and regular FYL2X is called. Note 5: The following opcodes are reserved by Cyrix: D9D7, D9E2, D9E7, DDFC, DED8, DEDA, DEDC, DEDD, DEDE, DFFC. If a reserved opcode is executed, and unpredictable results may occur (exceptions are not generated).
Advancing the Standards
®
FPU Clock Counts