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HCF4096B
GATED J-K MASTER SLAVE FLIP-FLOP
s
s s
s s
s s
16MHz TOGGLE RATE (Typ.) at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4096BEY HCF4096BM1 T&R HCF4096M013TR
DESCRIPTION HCF4096B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4096B is a J-K Master-Slave Flip-Flop featuring separate AND gating of multiple J and K inputs. The gated J-K input control transfers
information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation.
PIN CONNECTION
September 2002
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 3, 4, 5 11, 10, 9 8 6 13 2 12 1 7 14 SYMBOL J1, J2, J3 K1, K2, K3 Q Q SET (S) RESET (R) CLOCK NC VSS VDD NAME AND FUNCTION J Inputs K Inputs Q Output Q Output Set Inputs(Active High) Reset Inputs(Active High) Clock Inputs Not Connected Negative Supply Voltage Positive Supply Voltage
TRUTH TABLE : SYNCHRONOUS OPERATION (S=0 R=0)
INPUTS BEFORE POSITIVE CLOCK TRANSITION J* L L H H
(*) : J=J1 · J2 · J3, K=K1 · K2 · K3
OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q NO CHANGE L H TOGGLES H L Q
K* L H L H
TRUTH TABLE : ASYNCHRONOUS OPERATION (J and K DON'T CARE)
INPUTS BEFORE POSITIVE CLOCK TRANSITION S L L H H
(*) : L = Vss, H = Vdd
OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q NO CHANGE L H L H L L Q
R L H L H
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FUNCTIONAL DIAGRAM
LOGIC DIAGRAM
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ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW °C °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V °C
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (µA) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 TA = 25°C Min. Typ. 0.02 0.02 0.02 0.04 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 -1.15 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 1 2 4 20 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85°C Min. Max. 30 60 120 600 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125°C Min. Max. 30 60 120 600 Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current
0/5 0/5 0/10 0/15 0/5 0/10 0/15
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
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Test Condition Symbol Parameter VI (V) 0/18 VO (V) |IO| VDD (µA) (V) 18 TA = 25°C Min. Typ. ±10-5 5 Max.
Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit
II
CI
Input Leakage Current Input Capacitance
Any Input Any Input
±0.1
7.5
±1
±1
µA
pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 250 100 75 150 75 50 100 50 40 7 16 24 70 30 20 Max. 500 200 150 300 150 100 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time
tPLH tPHL Propagation Delay Time (Set or Reset) tTLH tTHL Transition Time
ns
ns
fCL
Maximum Clock Input Frequency Clock Pulse Width
tW
3.5 8 12 140 60 40
MHz
ns 15 5 5
tr, tf
Clock input Rise or Fall Time
µs
tW
Set or Reset Pulse Width
tsetup
Data Setup Time
200 100 50 400 160 100
100 50 25 200 80 50
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
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TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM : PROPAGATION DELAY TRANSITION AND SETUP TIME
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WAVEFORM : CLOCK PULSE, RISE AND FALL TIME
TYPICAL APPLICATION : D - TYPE FLIP FLOP
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Plastic DIP-14 MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001A
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SO-14 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 ° (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45° (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13G
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