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Now downloading free:ST 4096


Download ST 4096 docs - Electronic circuits, electronic components datasheets and schematics


File information:
File name:4096.pdf
Size:182 kB
Extension:
MD5:743c14e77e33d4548b370df0fdafa914
Mfg:ST
Model:4096 🔎
Original:CMOS 4xxx 🔎
Descr:GATED J-K MASTER SLAVE FLIP-FLOP
Group:Electronics > Components > Integrated circuits >
Uploaded:20-05-2005
User:dupator
Multipart:No multipart

Information about the files in archive:
Decompress result:OK
Extracted files:1
File nameText
4096.pdfHCF4096B GATED J-K MASTER SLAVE FLIP-FLOP s s s s s s s 16MHz TOGGLE RATE (Typ.) at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4096BEY HCF4096BM1 T&R HCF4096M013TR DESCRIPTION HCF4096B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4096B is a J-K Master-Slave Flip-Flop featuring separate AND gating of multiple J and K inputs. The gated J-K input control transfers information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operat

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