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HCF4034B 8 STAGE STATIC BIDIRECTIONAL PARALLEL/SERIAL INPUT OUTPUT BUS REGISTER s s s s s s s s s s s BIDIRECTIONAL PARALLEL DATA INPUT PARALLEL OR SERIAL INPUTS/PARALLEL OUTPUTS ASYNCHRONOUS OR SYNCHRONOUS PARALLEL DATA LOADING. PARALLEL DATA-INPUTS ENABLED ON "A" DATA LINES (3-STATE OUTPUT) DATA RECIRCULATION FOR REGISTER EXPANSION MULTIPACKAGE REGISTER EXPANSION FULLY STATIC OPERATIONAL : DC to 5MHz (Typ.) at VDD = 10V QUIESCENT CURRENT SPECIF. UP TO 20V INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" SOP ORDER CODES PACKAGE SOP TUBE HCF4034BM1 T&R HCF4034M013TR DESCRIPTION HCF4034B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in SOP packages. HCF4034B is a static eight-stage parallel-or serial-input parallel-output register. It can be used to : 1) bidirectionally transfer parallel information between two buses ; 2) convert serial data to parallel form and direct the parallel data to either PIN CONNECTION of the two buses ; 3) store (recirculate) parallel data, or 4) accept parallel data from either of the two buses and convert the data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/ S), A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARALLEL/ SERIAL (P/S). Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) depending on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided. All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow September 2002 1/15 HCF4034B synchronous or asynchronous data transfer from master to slave. Isolation from external noise and the effects of loading is provided by output buffering. PARALLEL OPERATION - A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock, provided the A/S input is low. If the A/S input is high, the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs) ; a low A/B signal reverses the direction of data flow. The AE-input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are IINPUT EQUIVALENT CIRCUIT enabled only when this signal is high. Data storage through recirculation of data in each register stage is accomplished by making the A/B signal high and the AE signal low. SERIAL OPERATION - A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is i