Text preview for : 4510.pdf part of ST 4510 PRESETTABLE BCD UP/DOWN COUNTER
Back to : 4510.pdf | Home
HCF4510B
PRESETTABLE BCD UP/DOWN COUNTER
s
s
s s
s s s
s s
MEDIUM SPEED OPERATION : 8 MHz (Typ.) at 10V SYNCHRONOUS INTERNAL CARRY PROPAGATION RESET AND PRESET CAPABILITY STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIF. UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
ORDER CODES
PACKAGE DIP TUBE HCF4510BEY T&R
DESCRIPTION HCF4510B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP package. It is a PRESETTABLE BCD UP/DOWN COUNTER consists of four synchronously clocked D-type flip-flops (with a gating structure to provide T-type flip-flop capability) connected as a counter. This counter can be cleared by a high level on the RESET line, and can be preset to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. This device will count out of non-BCD counter states in a maximum of two clock pulses in the up mode and PIN CONNECTION
a maximum of four clock pulses in the down mode. If the CARRY IN input is held low, the counter advances up or down on each positive going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY OUT of a less significant stage to the CARRY IN of a more significant stage. HCF4510B can be cascaded in the ripple mode by connecting all clock inputs in parallel and connecting the CARRY OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY OUT must be gated with the clock, and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage.
September 2002
1/11
HCF4510B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 4, 12, 13, 3 6, 11, 14, 2 15 10 5 7 9 8 16 SYMBOL PRESET ENABLE P1 to P4 Q1 to Q4 CLOCK UP/DOWN CARRY-IN CARRY-OUT RESET VSS VDD NAME AND FUNCTION Preset Enable Input Inputs Outputs Clock Input Up/Down Control Input Carry Input Carry Output Reset Input Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
CL X CARRY-IN (Cl) H L L X X
X : Don't Care
UP/DOWN X H L X X
PRESET ENABLE L L L H X
RESET L L L L H
ACTION NO COUNT COUNT UP COUNT DOWN PRESET RESET
X X
2/11
HCF4510B
LOGIC DIAGRAM
TIMING CHART
3/11
HCF4510B
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW °C °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V °C
4/11
HCF4510B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (µA) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25°C Min. Typ. 0.04 0.04 0.04 0.08 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 ±10-5 5 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 5 10 20 100 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85°C Min. Max. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125°C Min. Max. 150 300 600 3000 Unit
IL
Quiescent Current
µA
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
±0.1
7.5
±1
±1
µA
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
5/11
HCF4510B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 200 100 75 210 105 80 240 120 90 125 60 50 320 160 125 100 50 40 4 8 11 Max. 400 200 150 420 210 160 480 240 180 250 120 100 640 320 250 200 100 80 ns Unit
tPHL tPLH Propagation Delay Time Clock to Q Output tPHL tPLH Propagation Delay Time Preset or Reset to Q Output tPHL tPLH Propagation Delay Time Clock to Carry Out tPHL tPLH Propagation Delay Time Carry in to Carry Out tPHL tPLH Propagation Delay Time Preset or Reset to Carry Out tTHL tTLH Transition Time
ns
ns
ns
ns
ns
fMAX
Maximum Clock Frequency Clock Pulse Width
tW
tREM (1)
Preset Enable or Reset Removal Time Clock Rise or Fall Time
2 4 5.5 150 75 60 150 80 60
MHz
ns
ns 15 5 5
tr , tf (2)
µs
tsetup
Carry in Setup Time
tsetup
Up/Down Setup Time
tW
Preset Enable or Reset Pulse Width
130 60 45 360 160 110 220 100 75
ns
ns
ns
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C. (1) Time required after the falling edge of the reset or preset enable inputs before the rising edge of the clock will trigger the counter (similar to setup time) (2) If more than unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.
6/11
HCF4510B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)
7/11
HCF4510B
WAVEFORM 2 : MINIMUM SETUP TIME (CI TO CLOCK) (f=1MHz; 50% duty cycle)
WAVEFORM 3 : PROPAGATION DELAY TIMES, MINIMUM RESET PULSE WIDTH (f=1MHz; 50% duty cycle)
8/11
HCF4510B
TIPICAL APPLICATIONS TYPICAL 16-CHANNEL, 10 BIT DATA ACQUISITION SYSTEM
TIPICAL APPLICATIONS CASCADING COUNTER PACKAGES
9/11
HCF4510B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
10/11
HCF4510B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com
11/11