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INTEGRATED CIRCUITS

DATA SHEET

TDA4691 Sync Processor with Clock (SPC)
Preliminary specification File under Integrated Circuits, IC02 September 1993

Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)
FEATURES Sync processor for horizontal (H) and vertical (V) sync pulses generated by internal 13.5 MHz oscillator Stable `On Screen Display (OSD)', if no input signal is present with free running internal oscillator; automatic turn over to locked oscillator, if input signal is available External clock oscillator can be used Standard 50/60 Hz signals are identified automatically Additional outputs for 13.5 MHz, composite sync, 50//60 Hz identification, signal identification (mute), super-sandcastle 12 V TTL compatible outputs (H, V, composite sync and 13.5 MHz) 3 different time constants for the PHI1 PLL: fast, normal and slow (T1, T2 and T3). Fast and normal time constant are set independent from each other Start of H-pulse definable by application Digital interference reduction for H and V signals Digital noise detector Time correction of non-standard H-pulses and equalizing pulses for optimum PLL control. GENERAL DESCRIPTION The TDA4691 is a bipolar integrated circuit for sync processing in 50/100 and 60/120 Hz TV sets, preferably in conjunction with the programmable deflection controller TDA9150. A line locked 13.5 MHz clock with several dividers and logic circuitry is available generating the horizontal and vertical sync outputs. The device can be assembled in a DIL20 or SO20 package. QUICK REFERENCE DATA SYMBOL Supply VP2 IP2 VP1 IP1 Ptot Inputs V20 Outputs V4 signal identification voltage 50/60 Hz voltage vertical output voltage horizontal output voltage clock output voltage no signal; 1 mA signal 50 Hz; 1 mA 60 Hz HIGH; -1 to 0 mA LOW; 2 mA V11 HIGH; -1 to 0 mA LOW; 2 mA V13 HIGH; -1 to 0 mA LOW; 2 mA ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER TDA4691 TDA4691T Note 1. SOT146-1; 1996 December 9. 2. SOT4163-1; 1996 December 9. PINS 20 20 PIN POSITION DIL SO MATERIAL plastic plastic - - input voltage RG = 1 k - 1 supply voltage supply current supply voltage supply current total power dissipation 4.5 - 7.2 - - 5.0 - 8.0 - 260 PARAMETER CONDITIONS MIN. TYP.

TDA4691

MAX.

UNIT

5.5 30 8.8 30 430

V mA V mA mW

2

V

0.3 VP1 0.3 VP1 VP2 0.8 VP2 0.8 VP2 0.8

V V V V V V V V V V

open - collector - - open - collector 2.7 - 2.7 - 2.7 - - - - - - -

V7

V10

CODE SOT146(1) SOT163(2)

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

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Fig.1 Block diagram.

Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)
PINNING SYMBOL BL INT1 GND1 SI INT2 SSC 50/60 Hz GND2 CS Vout Hout VP2 CLout SH VCOF Fi1 Fi2 VREF VP1 (C)VBS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION black level storage of sync separator integration for time constant switching ground for 8 V supply signal identification output integration for signal identification sandcastle output 50/60 Hz output ground for 5 V supply sync output V-output buffer H-output buffer supply 5 V clock-output buffer start of H-pulse current defining VCO frequency phase detector filtering phase detector filtering reference voltage supply 8 V input sync separator

TDA4691

Fig.2 Pin configuration.

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)
FUNCTIONAL DESCRIPTION (See block diagram Fig.1 and timing Figs 12 to 16) Sync separator Top-sync and blacklevel are stored and H and V sync pulses are sliced in the middle of both levels (50%). Sync-output buffer This circuit turns the current pulse from the sync separator into a TTL signal. Sync processing This circuit assures that phase comparison can operate correctly during V-pulses. Phase jumps initiated by alternating headpulses of VCR recorders are quickly recovered. The sync processing contains the functions H/2 suppression, sync extension and sync interruption. These three functions are only active if successive pulses have a minimum distance of 1.6 s. The H/2 suppression operates with a gate -15 s up to +14 s around the PHI1-reference and is necessary for suppression of the equalizing pulses. For sync interruption this gate is closed earlier if the detected sync is longer than 4.8 s. Only during V-pulses will the duration of the applied pulses be tested. If they are longer than 1.6 s they will be recognized as sync pulses and enlarged up to 4.6 s. Phase detector (PHI1) The phase detector has separate filters for the fast time constant T1 (pin 17) and normal time constant T2 (pins 17 and 16). The slow time constant T3 uses the normal time constant T2 with reduced control current. For reduction of H-pulse modulation the filter at pin 16 is switched off during sync time if normal time constant T2 is on. Thus H-divider This is a divider by 54. It is split into a prescaler :2 and a divider by 27. Out of this block several signals are taken for generation of H-frequently pulses in the H-logic block. These signals must have good timing. This is achieved by special synchronization. VCO 13.5 MHz The adjustment of the nominal frequency (13.5 MHz) is achieved at pin 15. The VCO control voltage is applied (from the phase detector) at pin 16. The control range can be adjusted by the current at pin 18. Pin 15 can be used to feed in an external frequency. Under these circumstances the internal VCO is switched off by application. The control voltage at pin 16 can be used to control the external VCO. VCO-buffer The VCO-buffer delivers a TTL compatible signal of 13.5 MHz to pin 13. ECL-prescaler This block consists of a :16 asynchronous prescaler. no frequency shifting of the oscillator is possible during sync. Time-constant switching This block contains a switch and an impedance converter (buffer). The switch connects the filters at pin 16 and 17 in parallel (normal time constant T2 or slow time constant T3). The buffer transfers the control voltage at pin 17 to pin 16 (fast time constant T1). Which of the 2 functions is active is determined by the blocks noise detector, V-logic or signal identification. H-logic

TDA4691

This block creates all pulses necessary for the SSC generator, the signal identification, the phase detector, the sync preparation and the V-divider. V-divider The V-divider consists of an asynchronous 10-bit divider and a decoder logic. The divider is clocked with twice the line frequency. The decoder circuit delivers the pulses necessary for the V-logic. V-logic In the V-logic the V-syncs from the sync separator are evaluated and noise reduced. Also certain operation states are switched ON and OFF. Additionally the reset pulse for the V-divider and the 50/60 Hz information is generated. H-pulse former The H-pulse starting point can be shifted in this stage, also the gate pulse of 2.4 s is generated for use in the digital noise identification block. H-pulse buffer In this circuit the line signal will be pre-synchronized by output signal of the :16 divider and synchronized by the 13.5 MHz clock. The buffer delivers TTL output signals. V-pulse buffer The signal out of the V-divider is synchronized with 13.5 MHz clock and converted to a TTL output level. Gap reference This circuit operates with the gap-principle and is stable with regard to temperature and supply voltage changes.

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)
50/60 Hz output This is an open-collector output, which is LOW if more than 287 lines/field are detected. SSC generator The SSC generator generates a 3 stage super-sandcastle pulse on an open-collector output, which is able to operate up to 12 volts. The blanking thresholds 2.5 V and 4.5 V are derived from the gap reference (point 16). Signal identification with Digital PLL (DPLL) The analog signal identification with output signal at pin 4 is completed with a DPLL. This PLL is able to lock on the separated sync although the 13.5 MHz VCO is not locked on the input signal. The ratio of the lock condition to the unlock condition influences the voltage at pin 5. The detector circuit of the analog signal identification block evaluates the voltages at pins 2 and 5. If the voltage at pin 5 reaches 4 V (most of the time the PLL is locked) pin 4 will be HIGH. The voltages at pins 2 and 5 together with the state of the V-logic set the operation state of the TDA4691. The TDA4691 is able to accommodate to different input conditions automatically. Some operation conditions can be set externally by influencing the voltages at pins 2 and 5: 1. Time constant T1 (fast) on: voltage at pin 2 is limited to 5 V (0 to 5 V). 2. Time constant T3 (slow) on: voltage at pin 5 is limited to 6.2 V (0 to 6.2 V). 3. Time constant T3 (slow) inoperative: voltage at pin 2 is limited between 4 V and 6.5 V. 4. Time constant T3 (slow) inoperative with input signal: voltage at pin 2 is limited to 6.5 V (0 to 6.5 V). 5. VCO frequency fixed to f0: pin 2 is set to ground (V2 < 1 V). Noise detector This block switches the time constant to `slow' if on standard signal a certain noise level is reached. This noise level is measured in a small window inside the sync pulse.

TDA4691

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP1 IP1 VP2 IP2 Ptot Tstg Tamb VESD II/O VI VI V6 V15 V16 V17 V18 supply voltage supply current supply voltage supply current total power dissipation storage temperature operating ambient temperature ESD-protection on all pins; note 1 currents on all pins except supply pins 3, 8, 12 and 19 voltage applied to pins 1, 2, 4, 5, 7, 14 and 20 voltage applied to pins 9, 10, 11 and 13 voltage applied to pin 6 voltage applied to pin 15 voltage applied to pin 16 voltage applied to pin 17 voltage applied to pin 18 PARAMETER 0 - 0 - - -25 0 300 -10 0 0 0 0 0 0 0 MIN. 9.0 40 5.7 50 650 +150 +70 - +10 VP1 VP2 13.2 5 5 5 5 MAX.

TDA4691

UNIT V mA V mA mW C C V mA V V V V V V V

Note to the limiting values 1. Equivalent to discharging a 200 pF capacitor through a 0 series resistor. THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air SOT146 (without heat spreader) SOT163 65 K/W 85 K/W THERMAL RESISTANCE

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Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

CHARACTERISTICS VP1 = 8 V; VP2 = 5 V; measured at Tamb = +25 C; unless otherwise specified; application see Figs 10 and 11; video input signal referenced to CCIR standard. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply (pins 19 and 12; all voltages are measured with regard to ground (pins 3 and 8)) V19 IP1 V12 IP2 Ptot V20(p-p) V20(p-p) RG I20 I20 SLH SLV supply voltage supply current supply voltage supply current total power dissipation 7.2 - same rise time as V19 4.5 - - - 0.1 - - - - - I9 = +1 mA I9 = -1 mA see Fig.3 see Fig.3 - 2.7 - 100 100 - - - - time constant T1 - 1.5 1.5 see VCO - - 2.9 -720 15.2 8.0 20 5.0 15 260 8.8 30 5.5 30 430 V mA V mA mW

Sync separator (pin 20) input voltage (peak-to-peak value) sync amplitude (peak-to-peak value) source resistor of generator current during sync current during remaining time AC coupled 1 - - -30 1 2 0.6 1 - - - - - V12 40 500 500 - - - - - 4.5 4.5 - - 3.1 -880 18.6 V V k A A

Black level (pin 1) slicing level H slicing level V 50 50 % %

Sync output (pin 9) V9 V9 CL t1 t2 f0 f0' I17 I17 I16 V17 V16 f0/V16 R15 V15 I15 gVCO no sync positive sync load capacitance time delay between pin 20 and pin 9 time delay between pin 20 and pin 9 0.3 - - 200 300 V V pF ns ns

Phase detector (pins 16 and 17) nominal sync frequency fosc : 864 = phiref current at sync time (fast and normal time constant) current at sync time (slow time constant) current at sync time filter 2 voltage filter 1 voltage VCO sensitivity 15.625 15.625 240 80 2 3 3 360 kHz kHz A A mA V V kHz/V

13.5 MHz VCO (pin 15) f0 defining resistor pin voltage (V19 dependent) current for 13.5 MHz transconductance at f0 see Fig.4(a) see Fig.4(a) 3.75 3 -800 - k V A kHz/A

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

SYMBOL f0/V16

PARAMETER VCO sensitivity

CONDITIONS 4% control range; depending on current at pin 18 -

MIN.

TYP. 360

MAX. -

UNIT kHz/V

Input of external oscillator (pin 15) V15 V15 Rint Cint V13 V13 V13 tr tf D13 CL T13 pin voltage AC pin voltage DC internal resistance internal capacitance see Fig.4(b) dependent on V19 see Fig.4(b) see Fig.4(b) I13 = -1 mA; V12 = 4.5 V I13 = 0 mA I13 = 2 mA; V12 = 5.5 V see Fig.5 see Fig.5 V13 = 1.5 V normal time constant T2; measured between lines 25 and 305 I11 = -1 mA; V12 = 4.5 V I11 = 0 mA I11 = 2 mA; V12 = 5.5 V see Fig.6 see Fig.6 see Fig.6 see Fig.6 see Fig.6 see Fig.6 1 - - - - 5 7 4 - - - 20 20 - - - 3 - - - V V k pF

13.5 MHz buffer (pin 13) clock HIGH level output voltage clock HIGH level output voltage clock LOW level output voltage rise time fall time mark-to-space ratio load capacitance jitter on clock output (peak-to-peak value) 2.7 2.7 0 - - 45/55 - - V12 V12 0.8 - - 55/45 40 2 V V V ns ns % pF ns

H-output buffer (pin 11) V11 V11 V11 tr tf t3 t4 t5 CL I14 t61 t62 t63 t64 V14 (t 61) H HIGH level output voltage H HIGH level output voltage H LOW level output voltage rise time fall time time relation pin 13 to 11 time relation pin 13 to 11 H-pulse width load capacitance 2.7 2.7 0 - - - 3 3.0 - - see Fig.6 see Fig.6 see Fig.6 see Fig.6 -1.1 -0.6 3.8 5.0 0 - - - 25 25 25 - 3.6 - - -1.3 -0.8 4.0 5.2 - V12 V12 0.8 - - 55 - 4.2 40 100 -1.5 -1.0 4.2 5.4 1 V V V ns ns ns ns s pF A s s s s V

Start of H-pulse (pin 14) current pin 14 time delay pulse between pin 20 and 11 time delay pulse between pin 20 and 11 time delay pulse between pin 20 and 11 time delay pulse between pin 20 and 11 voltage pin 14 (proportional to V19)

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

SYMBOL V14 (t 62) V14 (t 63) V14 (t 64) V10 V10 V10 tr tf t3 t4 t5 t6 CL VREF R18 f I18/1 fa I18/3 I18/3 V7 V7 I7 V6 V6 V6 V6 tw tw t2

PARAMETER voltage pin 14 (proportional to V19) voltage pin 14 (proportional to V19) voltage pin 14 (proportional to V19) V HIGH level output voltage V HIGH level output voltage V LOW level output voltage rise time fall time time relation pin 13 to 10 time relation pin 13 to 10 V-pulse width time delay between pin 20 and pin 10 load capacitance

CONDITIONS 2

MIN. 3.5 5 4

TYP. 2.4 5.5 - - - 25 25 25 - 320 16 -

MAX. 2.8 4.5 6 V V V

UNIT

V-output buffer (pin 10) I10 = -1 mA; V12 = 4.5 V I10 = 0 mA I10 = 2 mA; V12 = 5.5 V see Fig.6 see Fig.6 see Fig.6 see Fig.6 see Fig.7 see Fig.7 see Fig.7 2.7 2.7 0 - - - 3 280 12 - V12 V12 0.8 - - 55 - 350 20 40 V V V ns ns ns ns s s pF

Reference (pin 18) reference voltage control current defining resistor control range VCO current pin 18 (4%) adjustable control range current pin 18 (3%) current pin 18 (5%) 1.1 8 - - 3 - - 1.2 - 4 105 - 80 120 - 0.3 - - 1.3 30 - - 5 - - V k % A % A A

50/60 Hz output (pin 7; open collector; see Fig.8) output voltage pin 7; 50 Hz 287.5 lines/field = LOW output voltage pin 7; 60 Hz 287 lines/field = HIGH output leakage current I7 = 1 mA I7 = 2 mA 0 0 2.7 - 0.3 0.8 V19 50 V V V A

Sandcastle output (pin 6) burstkey pulse H-blanking pulse independent from Vsupply V-blanking pulse independent from Vsupply voltage pin 6 LOW pulse width burstkey; 50 Hz pulse width burstkey; 60 Hz time relation between pin 20 and burstkey at 6.5 V; see Fig.9 at 6.5 V; see Fig.9 see Fig.9 see Fig.9 9.5 4.3 2.3 0 4.0 3.3 2.2 10 4.5 2.5 0.2 4.3 3.8 2.5 12 4.7 2.7 0.8 4.7 4.1 2.8 V V V V s s s

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

SYMBOL t3 t4 t5 t5 t6 t6

PARAMETER time relation between pin 20 and blanking H-blanking time start time H-pulse pin 20 to stop time burstkey pin 6; 50 Hz start time H-pulse pin 20 to stop time burstkey pin 6; 60 Hz V-blanking pulse; 50 Hz V-blanking pulse; 60 Hz

CONDITIONS see Fig.9 see Fig.9 H-sync = 4.7 s; see Fig.9 see Fig.9

MIN. 3.5 - 8.0 7.5 - -

TYP. 4.0 11.8 9.0 8.6 -2.5 to +22.5 -3.0 to +17 - - - - 0.2 - -

MAX. 4.5 - 9.7 9.2 - -

UNIT s s s s lines lines

Integration (pin 5) V5 V5 no TV signal TV signal slow time constant on see Fig.16 see Fig.16 0 4 5 2 - 6.2 V V V

Signal identification (pin 4; open collector via R4 to V19 or V12) V4 V4 I4 V2 V2 V2 V2 V2 V2 voltage pin 4, if no signal is identified voltage pin 4, if signal is identified leakage current I4 = 1 mA I4 = 5 mA 0 0 - - - - - - - - - - - 0.3 0.8 V19 50 - - - - - - - - - V V V A

Integration (pin 2; see Fig.15) no signal at pin 20 noise at input pin 20 switching T3 to T1 (delay 7 fields) switching T3 to T1 (noise and signal at input pin 20) release V-divider hysteresis release time constant normal (T2) signal identification at pin 4 hysteresis V2 release noise detector 1.5 3 2.5 2.5 4 -0.2 5 -0.2 6.5 V V V V V V V V V

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.3 Sync output.

Fig.4 Pin 15 circuit for (a) internal VCO; (b) external VCO.

Fig.5 Clock output.

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Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.6 Time relationship of pin 10/11 to pin 13/20.

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Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.7 Time relationship pin 10 to pin 20.

Fig.8 50/60 Hz output.

Fig.9 Sandcastle output.

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Philips Semiconductors

Sync Processor with Clock (SPC)

15
(1) control range VCO 4%; see CHARACTERISTICS. (2) depending on H output shift; see CHARACTERISTICS.

VP (V)

R2 (k)

5

5.1

8

8.2 Fig.10 Application diagram.

Preliminary specification

TDA4691

September 1993

Philips Semiconductors

Sync Processor with Clock (SPC)

16 R2 (k) 5.1 8.2 Fig.11 TDA4691 with external VCO and prescaler.
(1) control range VCO 4%; see CHARACTERISTICS. (2) depending on H output shift; see CHARACTERISTICS.

VP (V)

5

Preliminary specification

TDA4691

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.12 H-timing overview.

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Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

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Fig.13 V-timing at 50 Hz operation.

Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

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Fig.14 V-timing at 60 Hz operation.

Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.15 Control of operation states by voltage at pin 2.

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.16 Control of signal identification (pin 4) and time constants by voltage at pin 5.

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Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

Fig.17 V-timing.

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Preliminary specification

Sync Processor with Clock (SPC)
PACKAGE OUTLINE DIP20: plastic dual in-line package; 20 leads (300 mil)

TDA4691

SOT146-1

D seating plane

ME

A2

A

L

A1

c Z e b1 b 20 11 MH w M (e 1)

pin 1 index E

1

10

0

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)

E

(1)

e 2.54 0.10

e1 7.62 0.30

L 3.60 3.05 0.14 0.12

ME 8.25 7.80 0.32 0.31

MH 10.0 8.3 0.39 0.33

w 0.254 0.01

Z (1) max. 2.0 0.078

26.92 26.54 1.060 1.045

6.40 6.22 0.25 0.24

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-05-24

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Philips Semiconductors

Preliminary specification

Sync Processor with Clock (SPC)

TDA4691

SO20: plastic small outline package; 20 leads; body width 7.5 mm

SOT163-1

D

E

A X

c y HE v M A

Z 20 11

Q A2 A1 pin 1 index Lp L 1 e bp 10 w M detail X (A 3) A

0

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.42 0.39 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)



0.9 0.4

0.012 0.096 0.004 0.089

0.019 0.013 0.014 0.009

0.043 0.055 0.016

0.035 0.004 0.016

8 0o

o

Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION

ISSUE DATE 92-11-17 95-01-24

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Preliminary specification

Sync Processor with Clock (SPC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

TDA4691
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow. The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.

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Preliminary specification

Sync Processor with Clock (SPC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values

TDA4691

This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

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