Agilent 5990-7513EN U4154A 4 Gb s AXIe-based Logic Analyzer Module - Data Sheet c20140926 [17] free download

File name 5990-7513EN U4154A 4 Gb s AXIe-based Logic Analyzer Module - Data Sheet c20140926 [17].pdf

Keysight U4154A AXIe-based Logic Analyzer Module Data Sheet 02 | Keysight | U4154A AXIe-based Logic Analyzer Module - Data Sheet Product description The Keysight Technologies, Inc. U4154A AXIe-based logic analyzer system combines reliable data capture with powerful analysis and validation tools to enable you to quickly and confidently validate and debug high speed digital designs operating at speeds up to 4 Gb/s. Figure 1A shows the small eyes associated with a DDR3 system operating at 1.4 V at 2133 Mb/s. The U4154A logic analyzer uses its unique eye scan capability to automatically place the sampling point in both time and voltage within the eye on each individual channel for optimal sampling reliability. Figure 1B shows the trigger setup to capture a burst of 8 Writes. The trigger sequencer operates up to 2.5 Gb/s, enabling accurate and precise triggering. Figure 1C and Figure 1D show the state listing and waveform for this capture. 12.5 GHz Timing Zoom with 256 K sample memory gives you simultaneous state and high-resolution timing measurements covering a time span of 20 us, which corresponds to 43680 clock cycles at a 2133 MHz clock rate. Figure 1B Figure 1C Figure 1A Figure 1D 03 | Keysight | U4154A AXIe-based Logic Analyzer Module - Data Sheet Product description (continued) Figure 2. Timing Zoom precisely measures the time between the rising edge of the clock and the rising edge of DQS in a DDR system. Available memory depth up to 200 M samples allows you to debug very complex problems where the cause and symptoms may be separated by several seconds. The amount of memory can upgraded after purchase; see "Upgrades" in "Ordering Information." No need to sacrifice sampling resolution to view more system activity. In timing mode, if your system has bursts of activity followed by times with little activity, you can use transitional timing along with the logic analyzer's deep memory to capture seconds to minutes of activity at 400 ps (2.5 GHz) sampling resolution. You also have the flexibility to increase the amount of time captured by excluding certain buses or signals from the transition detector, for example clock or strobe signals that add little useful information to the measurement. In State mode, use store qualification to save only states of interest into memory. The dual-sample mode has two benefits: For DDR memory signals up to 2.5 Gb/s, it will separate reads from writes, with automatic setup of the correct sampling positions for each. This mode also allows acquisition of state (synchronous) data at rates up to 4 Gb/s. When used in this mode, the data will appear in two labels. One label for rising edge and another for falling edge captures. The logic analyzer will be clocked with one edge of the system clock. Labels can be merged using the Keysight B4602A Si