Agilent DDR4 TdiVW VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate 5991-1761EN c20140918 [5 free download

File name DDR4 TdiVW VdiVW Bit Error Rate Measurement or Understanding Bit Error Rate 5991-1761EN c20140918 [5

Keysight Technologies DDR4 TdiVW/VdiVW Bit Error Rate Measurements or Understanding Bit Error Rate Measurements in DDR Application Note 02 | Keysight | DDR4 TdiVW/VdiVW Bit Error Rate Measurements or Understanding Bit Error Rate Measurements in DDR - Application Note Historically, DDR (double data rate) has defined its timing specifications with a belief of a zero bit error rate (BER). While a zero bit error rate is statistically not possible, timing budgets had enough margin to justify the method of specifica- tion and measurement. With each generation of DDR Synchronous Dynamic Random Access Memory (SDRAM), speeds increase, package sizes decrease, and power consumption decreases. (See Table 1). Added challenges come with these improvements of decreased design margins, signal integrity, and interop- erability. Latest DDR technology offers data rates of 3.2Gb/s or higher. Each picosecond now matters and can be the difference in passing and failing bits. At these high data rates, BER measurements are important in order to under- stand the true reliability of a system. Noise and jitter affect the signal integrity and its overall reliability. Measuring and understanding the components of noise and jitter can enable designers to minimize them on the overall system design to ensure valid and accurate data transfer. In this paper, we are going to take a look at the measurements of the timing data input valid window (TdiVW) and the voltage data input valid window (VidVW). Table 1. DDR technologies and key JEDEC specifications DDR standard DDR LPDDR or DDR2 LPDDR2 or DDR3 LPDDR3 or DDR4 mobile-DDR mobile-DDR2 mobile-DDR3 Specification JESD79E JESD209 JESD79-2E, JESD209-2B JESD79-3C JESD209-3 JESD79-4 JESD208 Operating vol