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Now downloading free:Samsung K4D551638F-TC

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Electronic circuits, electronic components datasheets and schematics

File information:
File name:256M GDDR SDRAM.pdf
[preview K4D551638F-TC]
Size:209 kB
Extension:PDF
Mfg:Samsung
Model:K4D551638F-TC 🔎 K4D551638FTC
Original:Revision 1.7 (June 2004) 🔎
Descr:Datasheets 4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronus DRAM - pag. 17
Group:Electronics > Components > Integrated circuits
Uploaded:02-08-2007
User:salvacolnome
Multipart:No multipart

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File name 256M GDDR SDRAM.pdf

Target Spec K4D551638F-TC 256M GDDR SDRAM 256Mbit GDDR SDRAM 4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM Revision 1.7 June 2004 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC 256M GDDR SDRAM Revision History Revision 1.7 (June 15, 2004) - Target Spec · Changed VDD/VDDQ of K4D551638F-TC33 from 2.8V + 0.1V to 2.8V(min)/2.95V(max) Revision 1.6 (March 31, 2004) - Target Spec · AC Changes : Refer to the AC characteristics of page 13 and 14. Revision 1.5 (March 18, 2004) - Target Spec · Added K4D551638F-TC33 in the data sheet. Revision 1.4 (February 27, 2004) - Target Spec · Added K4D551638F-TC36/40 in the data sheet. Revision 1.3 (December 5, 2003) · Changed VDD/VDDQ of K4D551638F-TC50 from 2.5V + 5% to 2.6V + 0.1V Revision 1.2 (November 11, 2003) · "Wrtie-Interrupted by Read Function" is supported Revision 1.1 (October 13, 2003) · Defined ICC7 value Revision 1.0 (October 10, 2003) · Defined DC spec · Changed part number of 16Mx16 GDDR F-die from K4D561638F-TC to K4D551638F-TC. Revision 0.1 (October 2, 2003) - Target Spec · Added Lead free package part number in the data sheet. · Removed K4D561638F-TC40 from the data sheet. Revision 0.0 (July 2, 2003) - Target Spec · Defined Target Specification - 2 - Rev 1.7 (June 2004) Target Spec K4D551638F-TC 256M GDDR SDRAM 4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES · 2.6V + 0.1V power supply for device operation · 2 DQS's ( 1DQS / Byte ) · 2.6V + 0.1V power supply for I/O interface · Data I/O transactions on both edges of Data strobe · SSTL_2 compatible inputs/outputs · DLL aligns DQ and DQS transitions with Clock transition · 4 banks operation · Edge aligned data & data strobe output · MRS cycle with address key programs · Center aligned data & data strobe input -. Read latency 3 (clock) · DM for write masking only -. Burst length (2, 4 and 8) · Auto & Self refresh -. Burst type (sequential & interleave) · 64m

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