InterM CA8320 free download

File name InterM-CA8320 pwrmix.pdf

SERVICE MANUAL P O W E R E D MIXER CA-8320 www.inter-m.com MADE IN KOREA NO: 9017040100 ELECTRICAL ADJUSTMENT PROCEDURE IDLE CURRENT A. Setting Set the mixer master volume minimum. B. Connection BCE Q113 Q115 BCE Q213 Q215 BCE Q313 Q315 VR301 VR101 VR201 AMP B'D Q114 ECB Q116 Q214 ECB Q216 Q314 ECB Q316 VOLT METER CONTENTS Electrical Adjustment Procedure Surround Processor 3 Specifications Electrical Parts List Top and Bottom View of P.C. Board Wiring Diagram Block Diagram Schematic Diagram Exploded View of Cabinet & Chassis / Mechanical Parts List Ass'y Drawing 1 2, 3, 4, 5, 6 7 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 18, 19, 20 21 22 23, 24, 25, 26, 27, 28 29, 30 31, 32 C. Adjustment Adjust VR101, so that the voltage through the between emitter of Q115 and Q116 become 5mV~6mV. Adjust VR201, so that the voltage through the between emitter of Q215 and Q216 become 5mV~6mV. Adjust VR301, so that the voltage through the between emitter of Q315 and Q316 become 5mV~6mV. 1 SURROUND PROCESSOR 3 OUTLINE YSS220(SP3) is an LSI which has surround capability by digital audio technology. The LSI has built-in A/D, D/A converters which enable digital sound processing for analog signals. With a 256k pseudo SRAM or SRAM connected, the LSI can process digital delay up to 512ms. PIN DESCRIPTION FEATURES - Built-in 15-bit floating ADC (L, R 2 channels) and DAC (FL, FR, RL, RR4 channels) enable digital processing for analog signals with 32kHz internal sampling frequency. - 4 channels except center output can output digital signals as well. With a DAC connected externally, it will be possible with up to 5 channels (FL, C, FR, RL, RR). - Hi-performance surround by mixing many echoes with using up to 512ms digital delay. - Preset mode for easy control by terminal setting. - Register control mode where it is possible to set various coefficients using microprocessor serial interface for original sound processing. - Internal DSP is a 24-bit x 13-bit high speed multiplier with 128 steps. - One 256k (32k x 8) pseudo SRAM or SRAM to be connected. - 12.288MHz (384fs) master clock. - 5V single power supply, Si-gate CMOS process. - 64-pin plastic QFP (YSS220-F) Note: Due to the nature of the product, the preset data cannot be disclosed although partially. 2 3 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name MD4 MD3 MD0 MD1 MD2 MCKO XO XI ER0/CSN ER1/SCKN ER2/CDI REV0 REV1 REV2 MUTEN ICN PRG MODE VSS AVSS CVA AORL AORR CHL AIL VDD AIR CHR AOFL/AOCE AOFR/AOCE AVDD CVB AVDD VDD TST0 TST1 I/O I/O I/O I/O I/O I/O O O I I+s I+s I+s I+ I+ I+ I+ Is I+ I+ ­ ­A ­A OA OA ­A IA ­ IA ­A OA OA ­A ­A ­A ­A I+ I+ Pin Function Description External RAM interface data terminal External RAM interface data terminal External RAM interface data terminal External RAM interface data terminal External RAM interface data terminal DOEN=`L': Master clock output (12.288MHz) DOEN=`H': Fixed to `L' X'tal oscillator terminal X'ta