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|5991-2567EN English _ 2014-08-03 _ PDF 2.37 MB c20140729 .pdf||Keysight Technologies
An Innovative Simulation Workflow
for Debugging High-Speed Digital
Designs Using Jitter Separation
This paper presents a new simulation workflow for jitter separation analysis. Jitter
separation is a very promising tool that quickly identifies the sources of signal integrity
degradation and thus enables easy optimization of a design to meet the low jitter
requirements of multi-gigabit high speed digital SERDES devices.
1.0 Introduction As data rates in high-speed products increase, identifying and solving signal
integrity problems becomes critical. Timing margins are becoming increasingly
tight. Several distinct effects influence the integrity of signals.
The deviation of a signal transition from its ideal time is defined as jitter.
Jitter becomes a probl|
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